LM22676: Output stage

Hello

I think that the capacitor you have in 1) is OK.

You should use the larger value rather than the 33uF if load transients are a concern.

The best way to evaluate the performance is to test on an EVM.

Thanks

Hello,

Thanks for your reply.

I just want to make sure - when using 68uF capacitor with 20% tolerance and a 150uHy inductor with 20% tolerance, there is a theoretical chance that both components are at their maximum value, and then the F0 pole will be at 1.3kHz.

The datasheet states that the pole should be at 1.5kHz to 15kHz for the loop stability.

From your answer I understand the if the pole is at 1.3 kHz the loop still will be stable. Am I right?

I can also put a 470uF capacitor, which brings the pole at nominal to 0.6kHz (I wanted at start to put large capacitance in order to stand large transients).

Will this value be ok?

Also, what about the ESR? Should I take into consideration any other parameter than the voltage ripple? 

Best regards,

Asaf Abraham

Hello Asaf,

You can try simulating this design in Webench with the output capacitor and the inductor at their theoretical maximum values and see what the resulting phase margin is. When I simulate this design, accounting for the 20% tolerance, I get low phase margin (~15degrees) indicating instability. Using the 470uF capacitor also results in low phase margin. 

I get a stable design using the 150uH inductor along with 2x 33uF output capacitors so this may be a good starting point.

Here is the link to the design: https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=D901F3ED129C2E34 

Like Frank mentioned, testing the design on an EVM will be the best indicator of whether the design will be stable or not. 

Regards,

Harrison Overturf

Hello Harrison,

Thanks for your answer.

From your answer I understand that when you simulated with 150uHy+20% and 68uF+20%, you got low phase margin.

1) What phase margin should I aim?

2) When I changed the inductor and the capacitor at the webench simulation you sent to 150uHy+20% and 68uF+20% I got about 77deg phase margin and 9.05kHz crossover frequency. Since you got at this situation 15deg phase margin, I think that I've made a mistake. Can you point me to the right direction?

3)  Also I noticed that when using 68uF/28mOhm capacitor, the phase margin was low (about 25deg), but when using 68uF/150mOhm, the phase margin was about 56deg. I concluded from this that the ESR of the capacitor is crucial for the stability of the system.

What is the relation between the ESR, the capacity and the phase margin.

In other words, what should be the ESR*capacity in order to get a stable system?

4) Does the ESR of the inductor crucial for the stability?

Best regards,

Asaf Abraham

Hi Asaf,

Try to aim for a phase margin of 45 degrees or greater. 

Did you change the ESR of the output capacitor when you simulated? When I got 15 degrees phase margin I used (180uH, 31.25mOhm, and 80uF, 7mOhm).

The ESR of the inductor does play a role in the stability of the design, however the impact that it has is dependent upon its relation to the other components in the circuit. For a detailed account of how the ESR of the inductor and the output capacitor impact the transfer function of the buck, please see this app note:

Buck Linear Family (ti.com).

In your case, I would recommend using Webench to select an output capacitor with an ESR that yields a phase margin at least 45 degrees then test this with your desired inductor on an EVM. 

Regards,

Harrison Overturf 

Hi,

Sorry for my late reply.

Your simulation helped!

Thanks,

Asaf