TPS54325: Questions for TPS54325PWPR and TPS54425PWPR

Jo,

Here are some resources for you and your customer:

Stability Analysis and Design of D-CAP2 and D-CAP3 Converter Part 1: https://www.ti.com/lit/an/slvaf11/slvaf11.pdf 

Stability Analysis and Design of D-CAP2 and D-CAP3 Converter Part 2: https://www.ti.com/lit/an/slvaf45/slvaf45.pdf 

Optimize Output Filter on D-CAP2 for Stability Improvement https://www.ti.com/lit/an/slva905/slva905.pdf  

Measuring the Bode Plot of D-CAP, D-CAP2, and D-CAP3 DC/DC Converters: https://www.ti.com/lit/an/sluaaf4/sluaaf4.pdf 

Accuracy-Enhanced Ramp-Generation Design for D-CAP3 Modulation: https://www.ti.com/lit/an/slva762a/slva762a.pdf (This is D-CAP3, but has background of how D-CAP2 works)

Regarding Inductor Selection:  For a 1.5V output, I would recommend a 1.8μH inductor, which falls between the 1.5μH inductor recommended for 1.2V and 2.2μH inductor recommended for 1.8V.

The average output impedance of the switching node at low frequency is the time-average of the Rdsons of the MOSEFTs.

For the TPS54325 that would be 120mΩ x Vout/Vin + 70mΩ x (1 - Vout/Vin)

For the TPS54425 that would be 65mΩ x Vout/Vin + 55mΩ x (1 - Vout/Vin)

Jo,

Yes, it would be possible to use a 1.5μH or 2.2μH inductor.

If selecting a lower inductor value, it would be recommended to increase the output capacitance inversely with the reduction in inductor value.

For example, when selecting a 1.5μH inductor rather than a 1.8μH inductor, increase the recommended output capacitor range 20%.  This prevents the faster current response of the lower inductor from creating an instability with the output capacitance.

While a larger inductor can allow for a lower output capacitance, it does not add the risk of instability they way a lower inductor does.

Hi Jo,

Since US is in holiday now, I'll help Peter to answer this question according to my understanding first.

1. The shaded area reflect where the difference will happen between the measured bode plot and the calculated model.

The calculated model of app note SLVA546 is based on small signal analysis with average switch model. The disturbance in each switching period is seen as the average disturbance and the model is used to reflect the changing between different switching period. There's no consideration of switching pulses in this model.

But in real bench test, the switching pulses is generated by the converter with frequency fsw. Compared with the ideal average model, that can be seen as using pulses signal with frequency fsw to sample an average model. Based on Shannon sampling theorem, if signal frequency is smaller than half of the sampling frequency, the sampled signal can reflect original signal. So for the real bode plot test, the gain/phase curve in the frequency range smaller than 1/2*fsw is same as the calculated average modelling results.

That means, bode plot of calculated model with frequency<fsw/2 can reflect the real bench test results.

2. It's same for D-CAP2. For the read phase margin and gain margin, please refer to the real bode plot test results rather than calculated results. In real test, if you cannot find the point that phase crossing 0degree, you can expand the measured frequency range in bode plot test. And the bode plot test will finally cross 0degree due to the phase drop effects with delay factor.

Thanks,

Andrew

Jo,

Andrew Xiong is correct on both point.

The application note is comparing the time-averaged, linearized model for D-CAP2 with measured results.  Since the time-averaged, linearized model is only accurate to 1/2 of the switching frequency, the measured data above 1/2 the switching frequency has been shaded..

One of the aspects of Constant On-Time Control, which D-CAP2 is a type of, is that the switching frequency increases with increased stimulation.  It is not uncommon for D-CAP2 control loops, especially those with low inductance and low output capacitance to have extremely high zero-phase crossover frequencies, at times into the multiple of Megahertz range.  This can cause automated test programs that stop the Frequency Response Analysis (FRA) testing prior to this zero-phase crossing to "fail" gain margin because the software can not find the zero phase crossing and thus can not calculate the gain margin.  This is not an issue with the design.  As Andrew points out, the best solution is to increase the frequency sweep range of the FRA test.

If the frequency range can not be increased for some reason, check the GAIN margin at the limit of the test.