This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] TPS6594-Q1: Residual Voltage Check

Part Number: TPS6594-Q1

How does the residual voltage check work?

  • How does the residual voltage check work?

    The residual voltage check is a utilization of the short circuit detection circuit to determine if any residual voltage (any voltage greater than 150mV) exists on a regulator output.  When enabled the check will occur within the fixed state machine and prevent the PMIC from transitioning from the INIT state to the BOOT_BIST state.  This effectively causes the PMIC to ‘wait’ until any residual voltage dissipates before allowing the PMIC to transition to the mission states to execute a power on sequence.   If the PMIC must wait then an indication is provided via the interrupt, nINT.  The source of the interrupt can be interrogated through the serial interface which can be configured as I2C or SPI.   Since the residual voltage uses the short circuit detection circuit and logic, residual voltage fault will result in the BUCKn/LDOn_SC_INT bit being set.

    The residual voltage check will also occur when a regulator enable bit (BUCKn/LDOn_EN) changes from ‘1’ to ‘0’ and both the monitor and the residual voltage check are enabled.  This feature, to check the voltage after the powering down of a regulator, has limited application use and is not recommended.

     As part of the NVM configuration, the residual voltage should be enabled as part of the static settings.  The static settings define the PMIC register values after the settings have been copied from the NVM space to the user register space.  This copying of settings takes place in the INIT state, so if the residual voltage is enabled in the static settings the residual voltage check will take place before transitioning to the BOOT_BIST state.

     Disabling of the residual voltage check, to disable the feature during power down, requires instructions within the PFSM portion of the NVM configuration.  Disabling the residual voltage should be the first function of the PFSM.

     For further description of the Residual Voltage Checking refer to the product datasheet:

     https://www.ti.com/lit/ds/symlink/tps6594-q1.pdf#page=64

     https://www.ti.com/lit/ds/symlink/lp8764-q1.pdf#page=69

    ----------------------------------------------------------------------------------------------------------------------

    Looking for more help? [FAQ] List of FAQs for TPS6594-Q1, TPS6593-Q1, LP8764-Q1 PMICs