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UCC21750QDWEVM-025: About Short Circuit Clamping TEST CONDITION

Part Number: UCC21750QDWEVM-025
Other Parts Discussed in Thread: UCC21750-Q1

In the datasheet of UCC21750-Q1, there is three SHORT CIRCUIT CLAMPING items. (VCLP_OUT(H), VCLP_OUT(L), VCLP_CLMPI) (Page.10)

I want to know the meaning of TEST CONDITION in these items.

For, VCLP_OUT(H), I understood it as when OUTPUT level is low and the 500mA current flows through OUT pin, after 10us the OUTPUT voltage minus VDD equals to 0.9V (typical).

Is it right? Becuase I'm not sure about the short clamping circuit, I'm not sure if I understood this operation well.

Best regards,

Yoonjin Kim

  • Hi Yoonjin, 

    Referring to section 8.3.5 of the datasheet, this short circuit clamping diode works to keep OUTH, OUTL and CLMPI voltage slightly above VDD to protect the internal circuitry. This is to combat the high dv/dt caused by miller capacitance during short circuit conditions. 

    And your interpretation is correct - for Vclp_outh, when output is low and a high dv/dt causes 500mA current to flow into the OUTH pin, after 10us, the diode works to keep the OUTH pin at only 0.9V above VDD. 

    Hope this helps.