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TPS40400: I2C getting ack at wrong address

Part Number: TPS40400
Other Parts Discussed in Thread: TMS320DM8168

Hi All,

        We are using TPS40400 in our design for supplying AVS core supply to TMS320DM8168 processor. The address of the TPS40400 is programmed to 0x38(70 in octal) using resistors. The TPS40400 is connected to TMS processor through I2cWhen we run I2C probe command for  listing the connected devices in the Bus, we are getting acknowledgement at 0x0C along with the slave devices connected to the I2c bus (Including 0x38). There is no slave with address 0x0c in our device. We found TPS40400 acknowledging for 0x0C. This will happen only one time even if we do I2c probe multiple times, can anybody explain this? .

Below I am attaching the images captured when device acknowledge at 0C with data 0x70. 

when we disconnect Tps40400 from bus negative ack only getting for 0x0c

TPS40400_REMOVED

  •  

    The TPS40400 is ACKing Address 0x0C because it supports the Alert Response Address (ARA) feature of SMBus.  A device with an ALERT for the system will ACK the Alert Response Address (ARA, 0x0C) and respond with it's address as a data byte.  Once it has responded with its address, it will clear the alert, which is why it is only responding once to address 0x0C

    If you need more information about SMBus or PMBus go to:

    http://www.smbus.org

    http://www.pmbus.org 

  • I greatly appreciate your response.

    1. But according to the SMBus spec. the device will respond to 0C only if there is interrupt/Fault. So is this acknowledgement we got for 0x0c is due to   valid fault in the IC? . Can I get the list of all fault conditions the IC can generate?. So that I can check which fault the device is generating.
    2. Also the device responds with its address as data, here we set the address of TPS as 70 in octal means 38 in hex. but  when we probed, the data transferred is 0x70 instead of 0x38
  • The response address is in the bits [7:1] position, with bit zero being a read/write bit, so address 0x38 will produce an address byte of 0x70 or 0x71 depending on read versus write.

    Read out the STATUS_BYTE (0x78) and STATUS_WORD (0x79, two bytes) values to see what warning has been set.

    Then you can check the associated STATUS_BYTE to see what warning or fault has been triggered in registers 0x7A - 0x80 for specific details.  Most likely the warning is in STATUS_CML - which is 0x7E

  • We have checked the STATUS_BYTE, STATUS_WORD and found that the issue is with the STATUS_CML(6th bit showing invalid/unsupported data). Do you know why this is happening. This issue occur only for a single time when we test multiple times.

  •  

    Invalid or Unsupported data is flagged when there is a write attempt to a read only command value, or there is an attempt to write data to a command outside of it's programmable range.

    Check to see if you are sending any other Commands / Write Attempts to the part prior to reading address 0x0C that might be generating the invalid data warning.

    It only occurs a single time because reading from the Alert Response Address clears the Alert until a new Alert is generated.  Once the Alert is cleared, the TPS40400 no longer responds to address 0x0C until it has a new alert.

  • As per Instruction we have checked whether there is any write attempt but we haven't found any write. Below I am sharing the terminal screenshots and the output that we got from the logic analyzer.

    logic_analyser_op.txt
    read to 0x00 nak
    read to 0x02 nak
    read to 0x03 nak
    read to 0x04 nak
    read to 0x05 nak
    read to 0x06 nak
    read to 0x07 nak
    read to 0x08 nak
    read to 0x09 nak
    read to 0x0A nak
    read to 0x0B nak
    read to 0x0C ack data: 0x70
    read to 0x0D nak
    read to 0x0E nak
    read to 0x0F nak
    read to 0x10 nak
    read to 0x11 nak
    read to 0x12 nak
    read to 0x13 nak
    read to 0x14 nak
    read to 0x15 nak
    read to 0x16 nak
    read to 0x17 nak
    read to 0x18 nak
    read to 0x19 nak
    read to 0x1A nak
    read to 0x1B nak
    read to 0x1C nak
    read to 0x1D nak
    read to 0x1E nak
    read to 0x1F nak
    read to 0x20 nak
    read to 0x21 nak
    read to 0x22 nak
    read to 0x23 nak
    read to 0x24 nak
    read to 0x25 nak
    read to 0x26 nak
    read to 0x27 nak
    read to 0x28 nak
    read to 0x29 nak
    read to 0x2A nak
    read to 0x2B nak
    read to 0x2C nak
    read to 0x2D nak
    read to 0x2E nak
    read to 0x2F nak
    read to 0x30 nak
    read to 0x31 nak
    read to 0x32 nak
    read to 0x33 nak
    read to 0x34 nak
    read to 0x35 nak
    read to 0x36 nak
    read to 0x37 nak
    read to 0x38 ack data: 0xFF
    read to 0x39 nak
    read to 0x3A nak
    read to 0x3B nak
    read to 0x3C nak
    read to 0x3D nak
    read to 0x3E nak
    read to 0x3F nak
    read to 0x40 nak
    read to 0x41 nak
    read to 0x42 nak
    read to 0x43 nak
    read to 0x44 nak
    read to 0x45 nak
    read to 0x46 nak
    read to 0x47 nak
    read to 0x48 ack data: 0x1B
    read to 0x49 ack data: 0x1E
    read to 0x4A nak
    read to 0x4B nak
    read to 0x4C nak
    read to 0x4D nak
    read to 0x4E nak
    read to 0x4F nak
    read to 0x50 ack data: 0xFF
    read to 0x51 nak
    read to 0x52 nak
    read to 0x53 nak
    read to 0x54 nak
    read to 0x55 nak
    read to 0x56 nak
    read to 0x57 nak
    read to 0x58 nak
    read to 0x59 nak
    read to 0x5A nak
    read to 0x5B nak
    read to 0x5C nak
    read to 0x5D nak
    read to 0x5E nak
    read to 0x5F nak
    read to 0x60 nak
    read to 0x61 nak
    read to 0x62 nak
    read to 0x63 nak
    read to 0x64 nak
    read to 0x65 nak
    read to 0x66 nak
    read to 0x67 nak
    read to 0x68 nak
    read to 0x69 nak
    read to 0x6A nak
    read to 0x6B nak
    read to 0x6C nak
    read to 0x6D nak
    read to 0x6E nak
    read to 0x6F nak
    read to 0x70 nak
    read to 0x71 nak
    read to 0x72 nak
    read to 0x73 nak
    read to 0x74 nak
    read to 0x75 nak
    read to 0x76 nak
    read to 0x77 nak
    read to 0x78 nak
    read to 0x79 nak
    read to 0x7A nak
    read to 0x7B nak
    read to 0x7C nak
    read to 0x7D nak
    read to 0x7E nak
    read to 0x7F nak
    

     So seems like the issue we seen is not due to illegal write attempt. Since write not happening here. Also we able to recreate the issue by attempting to write to a read only register. Is there any other reasons that might possibly cause the same issue?  

  • I will need to check on what other communications issued could trigger a invalid data.

    Are you running through this detection script multiple times?

  • Yes but it's not as a script, we are running the command "I2C probe" multiple times in U-boot.

  • Are you seeing this error on the first or second run through U-boot?

    PMBus considers a device receiving it's address with a read-bit at the start of a transaction a communications error, and that may be what is causing the invalid data flag.  I can check.

  • Yes we see this error on the second run in U-boot. 

  • Hi Vishnu,

    Peter will reply you by tomorrow.

  •  

    That is what it is.  The routine is using receive byte, which starts a transaction with the device address followed by a Read Bit, which is an invalid transaction type per the PMBus standard.  That is creating the invalid data flag.

    You can clear the flag by sending a "Clear Faults" to the TPS40400 device.  Clear Faults is a Send Byte (Device Address + Write Bit, Command Code = 0x03, no data bytes) to clear the warning from STATUS_CML.

  • We have tested this using I2Cdetect in kernel but we rarely found 0C acknowledging. Do you know why this is different in u-boot and in kernel. In U-boot the issue is created second time when we run i2c probe, but in kernel, this is not found. We are not saying that the issue isn't created, it shows up sometimes only. Also we have probed the SMBALERT# pin, this pin is always in low state.

  •  

    The -r option in your root command is using the "Read Byte" protocol instead of the receive byte protocol.

    Receive Byte sends Address + Rd and expects immediate data returned from the part.

    Read Byte sends Address + Wr followed by a Command Code or I2C register address and a repeated start, then Address + Rd 

    The prior instance, receive byte, is a PMBus transaction error

    The laster instance, Read Byte, is not a PMBus transaction error 

    If you try running i2cdetect without the -r option from kernel, I think you will see the same issue.  If you can run the i2cdetect with the -r option in U-boot, you likely wont see the problem.