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UCD90320: Behavior check for UCD90320

HSU HANWEN
Intellectual 290 points
Part Number: UCD90320

Hi ;

1. Is it OK for V33A,V33D and Reset ramp up together?

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2. When I'm doing validation report, I found it take UCD90320 around 55ms from Reset is released to Enable, GPO and some LGPO to act.

Is this a normal value?

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If not, what's the correct time interval of them after Reset is released?

  • +1
    TI__Guru 58090 points

    Hi

    Yes 45-55ms is a typical case to finish the boot-up and initialization.

    Regards

    Yihe

  • 0 in reply to yihe
    Intellectual 290 points

    Hi Yihe:

    1. How long will LGPO take when logic of it is changed?

    2. What status of LGPO during logic of it is chagned?

  • +1 in reply to HSU HANWEN
    TI__Guru 58090 points

    Hi

    1. The LGPO is processed at 100us period.

    2. the change is instant when it is processed. there is no middle state.

    Regards

    Yihe

  • 0 in reply to yihe
    Intellectual 290 points

    Hi Yihe:

    1. While UCD90320 is boot-up and initialization, no matter GPIs are set as active high or low, they're all high impedance right?

    2. While UCD90320 is boot-up and initialization, what status & impedance will following condition have?

    (a) GPOs are set as output high

    (b) GPOs are set as output low

    (c) LGPOs are set as output high

    (d) LGPOs are set as output low

    3. After UCD90320 finished bootup and initialization, what status & impedance will above condition have?

  • 0 in reply to yihe
    Intellectual 290 points

    Hi Yihe:

    *PCIE_CLK_SEL is LGPO with logic "invert of PCIE_MFG".

    *There're two voltage dividers with same value and Rupper is connected to P3V3. PCIE_CLK_SEL is connected between these two voltage dividers.

    -

    As first diagram shows, UCD90320 on my board took around 55ms for initialization.

    But if we zoom in, as 2nd diagram shows, it'll be low for around 380us.

    Is this a correct timeline?

  • +1 in reply to HSU HANWEN
    TI__Guru 58090 points

    Hi

    That's correct. 

    During that 55ms, the IO is under Hi-Z, so you can see that the voltage is somewhere between 3.3V and 0. after the initialization, UCD starts to configure drive the IO based on the logic so it went low and back to high.

    Regards

    Yihe