TPS55288: Short Circuit Fault, cannot find the short

Hi Grant.

Thank you for reaching out on E2E.

DO you mean the device Vout could rises to correct 15.5V? Is there any switching waveform that you could share with us.

Hi Zach,

Thanks for offering help. The goal is to make Vout (called BoostOUT in schematic) 14.7V, it is generally around .7V because of HICCUP mode from the short circuit fault. I have attached a scope capture of SW1. Since HICCUP mode is activated whenever it is turned on, there are two waveforms one for the 76ms that switching is turned off and one for the 4ms that it is turned on. The first waveform is with switching on and the second is with it off, so there is just a constant voltage. Let me know if you need any more information and I will get it to you as soon as possible.

Hi Grant,

During the test, did you apply load at the BoostOUT node? Is the test done with or without load? The hiccup mode happens only when Vout is below 0.8V and average current limit is triggered.

Could you also share the layout?

Hi Zach,

Thanks for the input. Vin is able to bypass the buckboost controller to power the MCU, so the BoostOUT shouldn't have any load on it. I will try removing that bypass to see if I get different results. I have attached a screenshot of the layout around the IC, as I cannot give you the whole layout. 

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Hi Grant,

I would say the layout is very poor, might be the root cause to cause the problem. 

Suggest you to refer to the layout guideline app note and update the layout.

You could modify the R16 value to lower value, for example, 30kohm. And disable the Output current limit in register IOUT_LIMIT

Hi Zach,

Thanks for the feedback. I've made a list of changes that I would like to make but I would appreciate it if you could go over it and answer a few questions.

1) Shift C4, C5, and C6 closer Q1, and put vias to bottom layer (GND plane) near them

2) Move R10 closer to Q2 Gate

3) Generally add a lot of vias to GND to shorten GND paths

I was wondering if you had any other specific advise related to layout? I was reading through the layout guide and I think that the output power loop is already minimized as C9 is very close to the IC, though I could find a way to move the other output capacitors closer as well if I need to, I didn't find that section of the guide to be super clear as it only showed the closest capacitor as part of the power loop. I was also confused because the guide said to keep SW1 and 2 traces very thin, but the example layout in the guide has large planes connected to both.

Hi Grant,

You can share the updated layout on E2E. I'll give you the comment based on the new layout.

SW1 and SW2 traces should be wide. You are correct.

Hi Zach,

I have attached an updated layout. I set copper planes to pour over nets, moved input capacitors closer to Q1 and added more vias to GND to shorten input power loop; I moved output capacitors to be closer to IC and GND plane with vias to shorten output power loop. Does this look better to you? please let me know if you have any more suggestions. I also switched R14 to a kelvin resistor, I don't think that will affect the IC but please let me know if it does.

Thanks for the help!

Hi Grant,

You still missed a lot of layout suggestions in the application note.

For example: 

Input capacitor C6 should be placed across Q1 Drain and Q2 Source to minimum Buck switching loop area.

Output capacitor C9 should be placed close to VOUT pin and PGND pin to minimum Boost switching loop area.

Widen the VCC trace width. Add 4 GND vias close to VCC capacitor C16.

Add vias close to pin 24 and pin 26.

Create a AGND plane for COMP, MODE, CDC, and etc. components.

...

Please go through the app note again.