Hi.
We are using a TLC5928 chip in a card reader application, to control 2 groups of RGB LEDs.
Each group of RGB LEDs is using 3 output pins of the TLC5928 chip, one pin per color.
Schematics show more outputs in use, but they are actually RFU and not connected.
RGB LEDs cathodes are connected to OUT0, OUT1 and OUT2 through some little resistors (~ 68 ohms)
RGB LEDs anodes are connected to VDD3V3.
To have more than 8 colors per group, some hardware is constantly updating the chip output
by clocking 16 bits of data, latching, clocking again 16 bits of data, latching, and so on.
Frequency is not very high, a new 16 bits value is latched every 1.3 millisecond.
SCLK frequency is around 13.9 kHz :
We are facing a strange chip behavior.
When we try to change RGB LEDs color and therefore switch from state { OUT0 active, OUT1 active, OUT2 inactive } to state { OUT0 inactive, OUT1 active, OUT2 inactive },
then the chip is shutting down all its output !
Here is this situation :
In <1>, last two bits of clocked value are both 1, asking for OUT1 active and OUT0 active.
After the latch pulse, green signal (OUT1) is still low = active as expected.
Then a color change occurs and a new 16-bits value is clocked.
For this new color, I need to have OUT0 disabled, and keep OUT1 enabled.
In <2>, last two bits of clocked value are 1 and 0, asking for OUT1 active and OUT0 inactive.
OUT1 is kept active as expected, and OUT0 went probably inactive (OUT0 not present on my screenshot).
In <3>, same 16-bits value is clocked to the chip as in <2> : last two bits of clocked value are 1 and 0, asking again for OUT1 active and OUT0 inactive (no change).
But for some unknown reason, OUT1 goes high (disabled) and also all other outputs !
I closely read chip datasheet, and I think all timings are respected.
The hardware that generate signals SIN and CLK updates SIN during the falling edge of CLK and keep it stable during the next rising edge of CLK.
Also CLK is kept low during the LATCH pulse.
As I said, timings are quiet slow : rising edge of CLK occurs ~ 36 microseconds after SIN being updated, which is much more than the requested values
in the datasheet.
I know that the internal on/off control shift register of the chip is replaced by LOD / PTW diagnostic bits on the rising edge of LATCH,
but I'm always latching only once, and there are always 16 CLK before the next latch pulse.
So I think I'm not having the bad situation were LOD /PTW diagnostic bits would be latched by error to the on/off control data register.
There is absolutely no way to recover from this situation, whatever value is clocked & latched into the chip.
Only a power-off and power-on can have the chip perform again normally.
Chip temperature is probably not involved. Tested with freezer spray : no change.
Project can run for for hours with no problems, and issue occurs only on some color transitions (not all transistions).
Also note that BLANK pin is unused and kept low.
Any help / hint would be greatly appreciated !
Best regards,
Fabrice GIRARDOT / DDM Hopt + Schuler / Germany
