TPS53647: TPS53647+ 4*CSD95490 solution，load chip side Ripple more than 40mVp-pk

Hello Peng,

I can't see the noise waveform with a time base of 1ms. I'd recommend taking scope shots at several different time scales so we can better see the noise waveform. Also, I'd recommend taking a scope shot of the SW node at a time base of ~1us.

Also, can you send your config file?

Thanks,

Travis

Hi Williams：

Thanks for the reply；

The PWM signal frequency is unstable（at 200Khz~2.8Mhz range），Ripple signal frequency is 65Khz；

CH3 ： TPS53647 to CSD95490 PWM 

CH4 ： load chip side Ripple

TPS53647  is look like manufacturers default config ，we only made hw external configuration（TPS53647+4 CSD95490.pdf）；

PS:  as follows is the chip derived config file，but i don‘t know unable upload；

Hi Williams：

1. can you check our schematic PDF,  For example TPS53647 external loop setup is right？

our demand output 0.89V，out current（4 phase） Normal 120A   MAX 157A；

2. as follows ，we try to debug loop setup， change R COMP and C COMPS value；

PWM signal frequency improved at 500Khz~700Khz range (our operating frequency setup 600Khz  );

But test chip ripple is not improve，still for 40mVp-p；

Thanks！

Hello Peng,

Are you using an active load to generate transient events? Looking at the PWM/Vout waveform, the converter seems sending PWM correctly. When Vout drops, the controller increases frequency to raise output voltage. It then remains stable for a moment, but then the output voltage rapidly rises without the controller sending extra PWM pulses. The controller compensates by skipping several pulses until Vout falls back into regulation, then the output stabilizes.

This looks like a response to a load transient.

Thanks,

Travis

Hi Williams：

Q: Are you using an active load to generate transient events? 

Peng --> yes, our MAC chip（BCM56770 core AVS） working  current is active load，load transients；

Load chip side ripple is to high，please ask how can we improve that ？ Debug TPS53647 loop setup？

Hi Williams:

Here is some info on how the compensation network operates, from page 99 of the datasheet.

Peng--> we try to setup multiple groups loop config debug loop setup（VSW output inductance 170uH to 220uH ）,  DCDC output side ripple has improve ，but load chip side ripple is not improve；

we will ask MAC load chip manufacturers this phenomenon；

Thanks!