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UCC28950: Current sharing imbalance - 2 stages

Iain Davis
Prodigy 110 points
Part Number: UCC28950
Other Parts Discussed in Thread: UCC39002, UC3902, PMP6712

Hello,

Consider a design similar to PMP6712.

I'd like to better understand the factors that affect the current balancing between each power stage in a 2-stage design.

For instance, we have a number of units that have fairly equal and consistent current sharing, then once and awhile we get a unit that is skewed in one direction (i.e., stage 2 is always x-amps higher than stage 1).

Are there ways to correct/tune a unit to promote better current sharing?

Thank you in advance,

Iain

  • 0
    TI__Mastermind 21825 points

    Hi Iain,

    Thank you for the query on UCC28950.

    You might to consider using UCC39002/ UC3902 load share controller.

    The following note shows an example implementation:

    https://www.ti.com/lit/an/slua128a/slua128a.pdf?ts=1669951524998

    The UCC39002 increases the output current of the module it is attached to by sinking a current at its ADJ pin through the NPN transistor. This current causes a voltage drop across RADJUST which 'fools' the UCC28950 controller into thinking the output voltage is lower than it should be. The UCC28950 then increases the module output voltage (by a small amount of course) to increase the output current. All of the UCC39002 controllers are using the same voltage at the LS bus as their reference so the currents are forced to be equal.

    Please let us know if you have any questions.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    Prodigy 110 points

    Hello Harish,

    Thank you for the detailed response!

    The UCC3902 is an excellent suggestion for a future improvement when we're able to re-spin the board.

    Would you have any insight into potential fixes that could be implemented on our existing design? (Which is very similar to PMP6712)

    Thank you in advance,

    Iain

  • 0 in reply to Iain Davis
    TI__Mastermind 21825 points

    Hi Iain,

    Thank you for the reply. I will check if there are any better methods for this and let you know.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    TI__Mastermind 21825 points

    Hi Iain,

    I tried to check for other solutions for current ibalance, but was not many approaches mentioned. But the following thread is an advice from our PSFB expert.

    https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/660372/ucc39002-pmp6712-share-ucc39002/2426250?tisearch=e2e-sitesearch&keymatch=UCC28950%2520AND%2520current%2520share#2426250

    Thank you

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    Prodigy 110 points

    Hello Harish,

    Thank you for the additional information, yet it does also seem to point back to using a load share controller... Are there any other methods that can be used on the system as-is? (i.e. trimming the gain resistors of the x2 opamps in the Master/Slave feedback path?)

  • +1 in reply to Iain Davis
    TI__Mastermind 29350 points

    Hello Iain, 

    Until Harish comes back to the office from some days out, I'll try to help you on this.

     Form what I could tell from the original PMP6712 design, the slave regulator's COMP voltage is supposed to follow the master's COMP and, all else being equal, it should generate the same output current level as a consequence. 

    I think the key assumption is that all else should be equal, and I suggest that sometimes it is probably not the case.  Although most of your systems end up sharing current well enough, those few exceptions have some inequalities that affect the current level and the source of the inequality needs to be uncovered.  

    I'm not sure that it is as simple as the tolerances of the gain resistors, although trimming them might overcome the actual inequality anyway. But the trimming becomes a manual operation which complicates production.  
    I think it is better to compare a "normal" working pair with an "abnormal" unequal pair, and probe all the feedback voltages and references and related signals to see where the largest divergence is from "normal" sharing operation. 
    Once that is identified, and if it is found to be a consistent deviation, then you can figure out what to do about it.

    For example, if most of the VREFs are the same, and the master/slave pairs share well, but one VREF is off quite a bit and that pair doesn't share well, then see if that happens every time a VREF is off.  On the other hand, if the VREFs vary quite a bit yet the sharing is still pretty good, then it's not the VREF, you need to look for something else.  The slave's COMP may be different due to variation in EA gain.  Or, the PWM ramps may not be the same, etc, etc. 

    You mentioned that the share ratio is always skewed in one direction, and that stage 2's current is always x-amps higher than stage 1.   Well, this is a clue to be used in the debug.  What happens if the two stages are swapped?  Does the imbalance follow the stage or stay with the "new" slave?  If it follows the converter stage, then the problem is in the converter.  If it doesn't follow the stage, it is external to both converters. 

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Prodigy 110 points

    Hello Ulrich,

    Thank you for the useful information, this is quite helpful.

    Regards,

    Iain