[FAQ] BQ76952: Mask registers for Alarm Raw Status

Hi Francis, 

Each bit in Alarm Raw Status can be selected whether it will be latched into Alarm Status when it asserts.  How the part knows which bits to latch is determined by the alarm mask.  When the part first powers up, it loads a mask register from Data Memory (Default Alarm Mask).  These bits can also be modified during operation without needing to change the Data Memory value by using the Alarm Enable command.  For example, if Default Alarm Mask was 0x0000, then no bit in Alarm Raw Status would be latched into Alarm Status if they asserted.  Then, for example, if you want the ALERT to assert whenever the FULLSCAN bit in Alarm Raw Status asserts, you can write to set the FULLSCAN bit in Alarm Enable.  Then after this, if the FULLSCAN bit asserts in Alarm Raw Status, it will be latched into the FULLSCAN bit in Alarm Status, and the ALERT pin will be asserted.  You can then clear the latched bit by writing a 1 to the FULLSCAN bit in Alarm Status.

Thanks,

Terry

Hi Francis, I'll address each question below:

1. Does mask register refer to Alarm Enable Register or Default Alarm Mask, SF Alert Mask A–C, PF Alert Mask A–D?
   1. Essentially yes, all of these registers are used to determine what bits will be latched by Alarm Status, which then determines if the ALERT pin will be asserted.  The Default Alarm Mask is what the device uses at powerup (for example, if you have this burned into OTP, the power will automatically use this setting for the mask without the uC needing to update it).  The Alarm Enable lets you modify the mask in use during operation.  The SF Alert Mask and PF Alert Mask are a second level of masking.  You can set selected bits in these registers, so when any of the selected safety alerts trigger, then if the MSK_SFALERT is set, then the MSK_SFALERT in Alarm Status will be set, and the ALERT pin will be asserted.  Similarly, if any selected PF alerts trigger, then if MSK_PFALERT is set, then the MSK_PFALERT in Alarm Status will be set, and the ALERT pin asserted.
2. If the bit in Alarm Raw Status isn't latched, whether the ALERT pin will output?
   1. The ALERT pin only outputs a signal based on an alarm if any bit in Alarm Status is latched.  It will not assert based on Alarm Raw Status.
3. TRM describe there is OR operation, but it seems AND operation: Alarm Raw Status set 1, mask register set 1, then Alarm Status set 1.
   1. The OR refers to any bit in Alarm Status.  If any one bit in Alarm Status is set, then the ALERT pin will be asserted, so this is an OR of all the bits in Alarm Status.  However, there is an AND operation that occurs between each Alarm Enable mask bit and the corresponding bit in Alarm Raw Status.
4. What is the principle of writing 1 to clear latched bit Alarm Status. Exclusive OR operation?
   1. If you write a zero to any bit, it does not clear any latched bit or change any unlatched bit to be latched.  There is only an operation when you write a 1 to a bit, then if that bit is set, it will be cleared.  If that bit is already 0, then it remains 0.
5. Why an earlier Alarm signal than fault protection is needed? Is it because the host needs to do some actions for battery system before the fault protection?
   1. Some customers prefer to get an alarm, then decide in their host FW whether to take action on this or not, instead of the device autonomously taking protective action.  The host may also be able to change system operation (such as slow a drone motor) to prevent a serious safety event from occurring, rather than waiting for the protection event to disable FETs, and the device suddenly becomes unpowered.

Thanks,

Terry

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