UCC2897A: PMP9656/ PMP3162 / PMP8380 design question

Simon,

Thanks for reaching out through E2E and for your interest in TI power management ICs. See below my answers to each of your questions.

Q1: What is the function of "D8", I see it on PMP3162 sch, but removed on PMP9656?

• Provides gate driver bias directly from the regulated converter output voltage OR from the AC transformer voltage. D3 is feeding a voltage to a linear regulator. Not sure why D8 was or was not included in one design vs another? It could be that bias will be supplied a bit longer from VOUT vs transformer AC voltage because of the large output capacitance - maybe this is important during a fault? 

Q2: in PMP9656 sch, "VDRV" Voltage is?

• D12 (6.8 V) - Vbe

Q2-1: The "VDRV" voltage is determine the SR-FET Gare-drive voltage level, right?  

• Correct

Q2-2: If I want to adjust the SR-FET Gate-drive Voltage level, how can I do?

• Since the SR drive voltage is determined by the transformer voltage, you are constrained to whatever the minimum input voltage is multiplied by the transformer turns ratio. If you want higher SR bias voltage at lower minimum input voltage, you need to develop a dedicated SR drive winding from the transformer. If you increase the SR drive voltage this way, you need to also be careful not to exceed the SR maximum gate drive during high input voltage operation.

In PMP8380 circuit, the SR-FET Gate drive circuit that is using Totem-Pole topology.

Q3: For cost effective consideration, may I use Totem-Pole circuit to replace UCC27511 drive circuit?

• Yes, but I like small IC gate driver circuits over discrete NPN/PNP totem pole. One thing to consider is that there is no UNLO associated with a discrete totem pole driver. The drive stage can try and produce drive signals when the bias may not be at the desired level - UVLO from a gate driver IC helps overcome this. Also, the SR gate drive timing may change when you transition from a dedicated gate driver IC to a discrete totem pole drive stage - pay attention to the propagation delay differences to assure you maintain proper SR timing.

Q3-1: If yes, which component parameter need to noted for higher output power design (12V/12A=>12V/21A)?

• Higher output current requires SR MOSFETs with lower Rds(on) which have higher gate charge requirements. A dedicated gate driver IC will provide the maximum desired drive current across the Miller plateau where it is need most to assure fast rise/fall times. When you know the gate charge you are trying to drive, you can select a gate driver suited to achieve the desired drive speed.

Q3-2: if not, could you recommend a suitable Gate-drive circuit to me for reference.

• Please refer to Fundamentals of MOSFET and IGBT Gate Driver Circuits. This app note is loaded with practical tips for designing all sorts of gate drive circuits.

Regards,

Steve M

Simon,

Responses to your open questions below:

Q2, Q2-1: It means D12 spec determeter the "VDRV" voltage, if I change the D12  to (8.2V), the Voltge level will become from 6.8V to 8.2V. At at the same time, the PWM level in OUT Pin of U1/ U4 will become from 6.8V to 8.2V, right? 

• the answer is maybe - changing the diode from 6.8 to 8.2 will clamp the the voltage at 8.2V, if the transformer turns ratio is defined to allow >8.2 on the secondary? Yes, the VDRV voltage is the bias voltage to the gate driver which determines the VGS voltage at the SR gate-to-source.

Q2-2: According to your reply, I have a little confuse for the Gate drive voltage of SR-FET? Is dermeterd by D12(x.xV) or transformer voltage?

• After the diode drop from D3, the transformer voltage is clamped by D12 then regulated by Q8. If the transformer voltage (determined by the turns ratio) after D3 is lower than the D8 zener voltage, then the VDRV voltage will be less than the D8 zener voltage. This is why there is another source for VDRV through D8. The two voltage are diode OR'd and the higher one prevails.

Regards,

Steve M