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BQ76952: BMS with BQ76952: Functionality of DCHG & DDSG in the AFE

Part Number: BQ76952
Other Parts Discussed in Thread: BQSTUDIO


I want to use the BQ76952 AFE to automatically control the charging(DCHG) and discharging(DDSG) FETs based on the faults and recovery from the faults. I'm thinking that I can do that by configuring DCHG Pin Config Register & DDSG Pin Config Register with pin function enabled (PIN_FXN1–PIN_FXN0 : 2 for selecting DCHG & DDSG). I've tried the configuration mentioned in the attached document. I'm able to create the faults and recover, but that doesn't seem to affect the DCHG and DDSG FETs. DCHG remains high all the time after the configuration even with faults. Please help me resolve this issue or correct me if my understanding of this functionality itself is wrong.

(BMS protection, faults, recovery has been independently tested for voltage, current, temperature, short circuit, etc)

FET Config.pdf

  • Hi Shashidhar, 

    The set-up for configuring the DCHG and DDSG registers are configured by writing a 2 (1 0 ) for the PIN_FXN1 & PIN_FXN0 bits to enable the use of these multifunction pins as DCHG and DDSG outputs. 

    However, there are more considerations to take into account as simply enabling the use of these outputs may not provide the desired behavior.

    If these pins are to drive low-side FETs, then the charge pump must be disabled in order to use these pins when the FET drivers are not used. This can be done by clearing both the Settings:FET:Chg Pump Control[CPEN] and Settings:FET:FET Options[FET_CTRL_EN]  bits.

    Otherwise, you should ensure that the CPEN and FET_CTRL_EN bits are set. 

    I would refer to the following sections in the BQ76952 TRM for guidance: 

    Table 5-8. FET Control Subcommands  note the commands that are not recommended for use when in DDSG / DCHG mode. 

    Section 6.7 DDSG and DCHG Pin Operation general operation information 

    *Table 13-13. DCHG Pin Config Register Field Descriptions for detailed description of the DCHG register bits

    *Table 13-14. DDSG Pin Config Register Field Descriptions for detailed description of the DDSG register bits

    Table 13-32. FET Options Register Field Descriptions  note the Bit 3 description. 

    Table 13-33. Chg Pump Control Register Field Descriptions note the Bit 0 description. 

    Hope this helps!


    -Luis Torres

  • Hello,

    I've been able to get the DCHG, DDSG functionality to work. My observations are as follows.

    DCHG & DDSG are on by default. Whenever FET enable is commanded DCHG & DDSG pins go OFF(my 1st problem).

    DCHG & DDSG turn ON whenever fault occurs and turn OFF once the fault recovery happens. But I need the same functionality with exact opposite polarity of the pins(i.e. ideal case where default ON and go OFF for faults, back to ON on recovery) I've tried changing the DCHG Pin Config & DDSG Pin Config Registers for the same by toggling OPT[5] bit. Doesn't seem to work at all. Is there anything in specific that should be looked into to do this?

  • Hi Shashidhar, 

    Unfortunately in my first reply I have made a mistake and would like to clarify that when using low-side FET drive the CTRL_FET_EN bit must be SET. 

    I am also looking into this behavior of the DCHG and DDSG  but I will need to do some additional testing and get back to you tomorrow with an answer. 


    -Luis Torres

  • Hi Shashidhar, 

    Upon closer examination, we determined that the Bit Register on BQStudio does not follow the FET state when using the reverse polarity (OPT5 bit set). However, if we measure the output of the DDSG and DCHG pin itself with a volt meter we observed that it did actually follow the desired behavior. 

    Can you please verify that this is the case by checking the pin output? 


    -Luis T