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tps40021 Sync

MG74275
Intellectual 290 points

Does this device sync to the positive or negative clock edge?

  • 0
    TI__Genius 17240 points

    Hi,

    Please refer to the synchronization section of the datasheet on page 14 and Figure 26 on page 22. It depends on how you apply the synchronization signal to the chip. Figure 6 gives two different configurations. Basically, when the voltage on ILIM/SYNC is pulled to less than 1 V, the part will not turn on high side FET until the voltage on ILIM/SYNC reaches (VDD - 1.0V).

    Please note 

    (1) The internal current sink on the ILIM/SYNC pin is from the pin to GND, not from VDD to this pin (not as shown on page 2).

    (2) Any stray capacitance on the ILIM/SYNC pin will slow down the rising slope of the voltage on it. To maximize this slew rate, minimize stray capacitance on this pin.

    (3) The duration of the synchronization pulse pulling ILIM/SYNC low shoud be between 50 ns and 100 ns. Longer durations may limit the maximum obtainable duty cycle.

    Regards,

    Na