My intention is to Hold the processor in RESET# when watchdog error is triggered. But the two JSON files attached are not achieving the same.
The file File1.json is resetting the CPU and it is also powers down the CPU and powers back up
The file File2.json is resetting the CPU and also it is powering down all the rails. I use GPIO4 as enable. When I re enable using GPIO going to 1 ->0 -> transition, I see that the
Is it possible to assert nRESETOUT and nRESETOUT_SOC, but keep the power ON ?
Also, I have WD_EN set to 1'b0 in the NVM. I enable the watchdog by software. When watchdog error occurs, If the system power cycles back as in File1 or I disable and re enable in File2 (via GPIO4), I do see that the WD_EN bit is set in the register 0x09 (Device addresss 0x12). Whe I power cycle, I get inital value as 0xBF (WD_EN = 1'b0). But after a watchdog error occurs, I do see that it is sticky. Even GPIO4 de assertion and assertion is not working
