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Original question:

TPS51362: Function of LP# and connection question

TPS51362: TPS51362 LP# setting questions enquiry

SHH
Mastermind 30616 points
Part Number: TPS51362

Hello Team,

Customer is in the process of designing with the TPS51362.

 Regarding  TPS51362, customer has conducted some tests as outlined below.

Could you please help clarify the impact of LP# on the Converter?

Vin = 20V, Vout = 1.8V

- LP# = always LOW, customer see no issues under both light and heavy loads, the output voltage maintains at 1.8V.

- During load pull, if LP# is pulled LOW, it doesn't affect the output voltage (maintains at 1.8V).

- With LP# = LOW and no load, IV5 measures 0.035mV/100mΩ which equals 350uA.

- With LP# = 5V and no load, IV5 measures 0.075mV/100mΩ which equals 750uA.

- Whether LP# = LOW or floating (5V), the output remains unaffected under both steady and transient loads.

 

Thanks for your assistance.

 

Best regards,

 

Scott

  • 0
    TI__Mastermind 18510 points

    Scott, If LP# active low, entering ULQ mode, some internal logic will be disabled, like integrator...then Iq will be smaller than LP# high, commonly impact a little for load regulation and light load efficiency, almost no impact for other performance.

    Yuchang

  • 0 in reply to Yuchang Zhang
    TI__Mastermind 30616 points

    Dear Yuchang,

     customer has observed some significant discrepancies in Asus's measurements of Iv5 in various LP# states when compared to the values provided in the datasheet.

     Would you be able to provide some clarification on this?

     For instance, with LP# set to LOW and no load, the Iv5 measurement is 0.035mV/100mΩ, which translates to 350uA. Similarly, when LP# is set to 5V without any load, Iv5 measures 0.075mV/100mΩ, equating to 750uA.

     

    Your guidance on this matter would be greatly appreciated.

     

    Best Regards,

    Scott

  • 0 in reply to SHH
    TI__Mastermind 18510 points

    Will close this thread due to we have email discussion.

    Yuchang