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TPS3436-Q1: Usage as redundant watchdog in a safety controller??

Part Number: TPS3436-Q1
Other Parts Discussed in Thread: TPS3436, TPS35-Q1, TPS36-Q1, TPS35, TPS36, TPS3435

We have to add a second watchdog to our safety related µC-system (TUEV-requirement)

It should hold outputs off, from power up (or reset via original WD) until and as long as it is properly triggered.

This should not be done by resetting the µC and expecting, it will behave properly afterwards, but directly in parallel to the µC and original WD.

But: I don't find a watchdog with such a behavior: Having a constant output level until being triggered.

Is it possible to use one of the new TPS3436-Q1 in such way? When would it be available?

Georg

  • Hello George,

    We plan to release TPS3436BFACADDFRQ1 part number soon. This device will hold the outputs deasserted after power up for 10 sec. If WDI trigger is not provided for 10 sec, the output will be asserted.

    If user provides WDI trigger during 10 sec, the device will start WD monitor feature. The WD timings will be set as per the capacitor and SETx pins.

    Let me know if this addresses your requirements.

    Thanks & regards,

    Shridhar.

  • Thank you for your quick response. Now, the TPS3436 has only one output, /WDO. And this output will change its status after 10s, even without triggering. So a defect µC-system could do dangerous actions after 10s ... What's the idea for not latching this status until a new power-up?

    May be, another device with separate /WDO and /RST would behave as we need. Or there is an easy workaround. But I didn't find some up to now.

    Thanks & regards

    Georg

  • Add-On:

    The TPS35-Q1 has separate /RESET and /WDO outputs and a orderable(?) option with latched outputs. The behavior after entering the latched state is described on page 24: /RESET remains high, /WDO remains low. (The described AND for both signals: high AND high = high??)

    But after power-up, /WDO will be high and /RESET changes from low to high as (as recommended for a reset). So again, /WDO changes the level after power up if not triggered.

    But the TPS35-Q1 is no a Window-WD!. TPS36-Q1 is the windowed version of TPS35-Q1 with the same behavior of /WDO.

    Georg

  • Hello George,

    The typical use case we come across is as follows:

    The 10s start up time of TPS3436BFACADDFRQ1 device allows for safe boot up of the MCU or processor. Thus ensuring the output WDO stays high during the boot process and does not interrupt the host boot process.

    Once the host boot up is complete, provides a WDI trigger to indicate the boot complete and then the device starts WD monitoring.

    If the host does not boot up in 10sec, the WDO is pulled low to RESET and initiate the boot process again.

    May I have a timing diagram of the behavior of the system and your expected WD behavior?

    Another option I can recommend is, the WD operation of this device can be disabled by setting SET[1:0] pins to 0b01.

    This can be the default configuration and the device WD will be disabled and /WDO = 1 until the SET pin values are 0b01. Even after 10 sec duration.

    Once the host is up and running, it can change the SET pin values to any other combination and WD operation will be enabled. After this /WDO output state will be decided based on WD operation.

    Hope this will address your requirement.

    TPS35 and TPS36 devices D pinout offer independent RESET and WDO output as these devices integrate supervisor functionality as well.

    TPS3435 and TPS3436 offer only WD functionality and hence they do not have independent RESET and WDO pins.

    Thanks & Regards,

    Shridhar.

  • Hello George,

    Vincezo has shared some additional information for your application over email.

    I will go through these and work on a solution. If needed we can get on a quick conference call.

    Thanks & Regards, 

    Shridhar.