BQ4050: Does EDV_PACK bit setting works as the TR description?

Andrew Su

Part Number: BQ4050
Other Parts Discussed in Thread: BQSTUDIO

dears,

BQ4050 TECHNICAL REFFERENCE refers that:

EDV_PACK (Bit 2): EDV Detection Method
1 = Pack-based
0 = Cell-based

but my customer found that the device might act vice versa, as when they set EDV_PACK =0, the real CEDVTHR shown in BQStudio might based on pack voltage as the attached picture:

the gg file is also attached here.

CN026-20230728.gg.csv

i also noticed the discussion about this bit in the earlier thread, but I did not find any evidence to support the conclusion "when EDV_PACK = 1, the gauge will multiply the EDV Threshold by the number of cells(=pack). This means that the TRM is correct".

what will BQ4050 do to determine CEDV voltage when EDV_PACK set to 0 or 1?

if any other parameter setting may affect the CEDV voltage?

please help to double check the concern from the customer, they need to confirm as soon as possible to meet project demand.

thanks a lot!

10 months ago

0 Shirish 10 months ago

TI__Guru 57747 points

I have assigned this thread to an expert

0 Jose Couso 10 months ago in reply to Shirish

TI__Mastermind 23576 points

Hello Andrew,

Which build version is the customer using? This behavior was fixed in build-20. If you provide me the srec, I can check the build version. Please provide the unseal keys if different to default ones.

Regards,
Jose Couso

0 Andrew Su 10 months ago in reply to Jose Couso

TI__Intellectual 940 points

CN026-20230728.srec

dear Couso,

please refer to the serc file.

thanks a lot!

0 Jose Couso 10 months ago in reply to Andrew Su

TI__Mastermind 23576 points

Hi Andrew,

I just realized I don't have a physical BQ4050 board. Can they just read the FW version and build in BQStudio?

Regards,
Jose Couso

0 Andrew Su 10 months ago in reply to Jose Couso

TI__Intellectual 940 points

dear Couso,

FYI:

0 Shirish 10 months ago in reply to Andrew Su

TI__Guru 57747 points

Jose is out of office and will reply when he is back on Monday

0 Wyatt Keller 10 months ago in reply to Andrew Su

TI__Guru** 102885 points

Hello Andrew,

It looks like the build is 20 (0x16) so it should have the fix. Can you share the log file as well so we can review the cell voltages?

Sincerely,

Wyatt Keller

0 Andrew Su 10 months ago in reply to Wyatt Keller

TI__Intellectual 940 points

BQ4050-GREENWAY-EDV issue-20230904.xlsx

dear Keller,

the attached is the log data. it is a 4s LiFePo4 battery, the imbalance at the end of the discharge made the cell voltage drop to 2400mv while the other cells were still around 2700mv, I checked the log data, the SOC did not drop to 0% at this time. so the customer think the EDV0 is reached ,as the EDV_PACK is set to 0, so the SOC should drop to 0% rather than keeping at 8% (the CEDV Smoothing config is set at 0d).

so the customer doubt even the EDV_PACK is set to 0, the EDV threshold is still decided by the pack voltage, that means the description of EDV_PACK bit is not correct in the technical manual reference.

please do help to double check.

thanks a lot!

0 Jose Couso 10 months ago in reply to Andrew Su

TI__Mastermind 23576 points

Hi Andrew,

The CEDV is set to 0x16C2, meaning the End of Discharge voltage is determined by cell voltage.

How was the CEDV profile 1 voltage table obtained? I am assuming the customer want SOC to report 0% around 2600mV. Meanwhile, the Fixed EDV 0 is set to 2400 V. Usually Fixed EDV 1 and 2 are set to 3% and 7% respectively.

I few things I suggest.

1- Set FIXED_EDV0 (Bit 5)

2- Set fixed EDV0 to a voltage where customer wants SOC = 0%. It makes sense to set it to 2657 mV in this case.

3- Set fixed EDV1 close to 2950mV and fixed EDV2 around 3000 mV. I hand calculated this by coulomb counting using the provided log.

Regards,
Jose Couso

0 Andrew Su 10 months ago in reply to Jose Couso

TI__Intellectual 940 points

dear Jose,

thanks a lot! i will ask the customer to modify parameters and redo the test.

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BQ4050: Does EDV_PACK bit setting works as the TR description?