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Original question:

UCC14240-Q1: Stiching Cap in hv gate drive applications

UCC14240-Q1: Making a UCC217xx + UCC14240-Q1 sandwich

certified powerpoint technician
Prodigy 145 points
Part Number: UCC14240-Q1

Hi, 


I was aware there was some testing being done on whether having UCC14240-Q1 and iso gate driver on exactly opposite sides (rather than side-by-side as in EVMs)
will have any negative consequences (possibly impact from UCC14240-Q1 EMI).

Could you share if there is any updated guidance on this? 

just curious because for my application it may be an option, and can promote a more compact layout. 

best

dimitri

  • 0
    TI__Expert 7526 points

    Hi Dimitri,

    Placing UCC1424-Q1 back-to-back/sandwich with isolated driver would lead to an increment on the heat for the device, especially when the device is running at full load. Also, when devices are back-to-back, the placement of ground vias becomes more difficult, decreasing the thermal dissipation for the device.

  • 0 in reply to Manuel Alva Hernandez
    Prodigy 145 points

    hello 

    i am not concerned about thermals tho and dont think u can say its gonna do thermal shutdown without knowing ambient or board temp. at a worst case board and ambient temp of 100C i would estimate around 13C of headroom to Min. rising TSD threshold.  as RthjA//RthjB~17C/W and Pdiss is roughly 1.6W


    Manuel Alva Hernandez said:
    Also, when devices are back-to-back, the placement of ground bias becomes more difficult, decreasing the thermal dissipation for the device.

    considering a 6+ layer board I dont think there will be any issue to have thick grounds. though it would likely not be in outerlayers 

    can you please tell me if this concept has been tested at all, particularly in regard to EMI concerns?

  • +1 in reply to certified powerpoint technician
    TI__Mastermind 25355 points

    Hi Dimitri....what's up?

    Let's back up a step here and please allow me to comment and correct. I agree that we should not be making assumptions or statements about thermal shutdown, especially since you have not shared any such concerns and we know nothing about your PCB design, ambient environment, switching frequency, load, etc.

    Your question was regarding back to back placement of a gate driver and IIB bias module and what concerns may arise. Specifically you asked about EMI. We have done a couple designs, 4-layer, 2oz copper PCB, with the driver and bias placed this way. We have difficulty placing the two devices in a perfect 1:1 sandwich arrangement. Instead of 100% overlap, think more like 40-60% overlap. Once you emphasize the priority of placing the driver caps and IIB module caps at the recommended locations, the routing, via placement, etc become difficult, especially if trying to achieve 100% overlap. 

    As a secondary consideration this does bring into play the concern of establishing a good thermal plan since you essentially have 2 heat sources placed back to back. As you know, the IIB modules rely on convection cooling which means we need a decent amount of solid copper GND plane top and bottom, connected thorough an array of thermal vias. Prioritizing the thermal portion of the PCB design will no doubt involve trade-offs against how much overlap between the driver and IIB module can be achieved and optimal capacitor placement. For some of the latest PCB design guidance for IIB modules, see section 9.5 of the UCC14141 data sheet here.

    EMI study for this arrangement has not been done. The transformer is well shielded but also you are placing a driver with high di/dt pulses directly in parallel with a converter modules operating at ~14MHz and the area beneath these ICs has no copper shielding. In a conventional SMPS design, this would be a no-no due to concern over coupling/corrupting gate drive signal, bias regulation, etc. With a 6-layer PCB, are you allowed to use inner PCB layer to overlap the iso region - such as what is done to make PCB internal layer stitch caps? If so, this could provide an extra degree of shielding between the gate driver/PWM and the IIB.

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 145 points
    Steven Mappus1 said:

    As a secondary consideration this does bring into play the concern of establishing a good thermal plan since you essentially have 2 heat sources placed back to back. As you know, the IIB modules rely on convection cooling which means we need a decent amount of solid copper GND plane top and bottom, connected thorough an array of thermal vias. Prioritizing the thermal portion of the PCB design will no doubt involve trade-offs against how much overlap between the driver and IIB module can be achieved and optimal capacitor placement. For some of the latest PCB design guidance for IIB modules, see section 9.5 of the UCC14141 data sheet here.

    thank u steve for this explanation. reading over the layout section of UCC14141 the recommendations are pretty strict, from what i see it recommends thermal vias on both top and bottom plus 2oz, and from the stitching vias i assume the bottom also needs to have a big copper pour for PGND. 

    Steven Mappus1 said:
    In a conventional SMPS design, this would be a no-no due to concern over coupling/corrupting gate drive signal, bias regulation, etc.

    i see this done with flyback transformers seems to work OK probably not best idea tho. 

    Steven Mappus1 said:
    ith a 6-layer PCB, are you allowed to use inner PCB layer to overlap the iso region - such as what is done to make PCB internal layer stitch caps? If so, this could provide an extra degree of shielding between the gate driver/PWM and the IIB.

    i could probably do that . but what abotu using inner layers ground?

    btw what does IIB mean? "Integrated Isolated Bias"??

  • 0 in reply to Steven Mappus1
    Prodigy 145 points
    Steven Mappus1 said:
    Hi Dimitri....what's up?

    not much you. anyways the design constraints just to achieve back to back appear to be too much of a PITA to justify beyond being cool. 

    i will abandon my dreams now. 

  • +1 in reply to certified powerpoint technician
    TI__Mastermind 25355 points

    Correct...IIB = "Integrated Isolated Bias"

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 145 points

    thank u steve have a good weekend.