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TPS7B86-Q1: About the design of TPS7B86-Q1 peripheral schematic diagram

Part Number: TPS7B86-Q1

Hi team,
1、Is there a more detailed schematic design reference diagram for the EN and PG pins?

2、When the TPS7B86-Q1 application circuit design output is 12V, are there any specific recommended values ​​for the R1 and R2 resistance values ​​of the FB pin?

  • Hi Guohai Lin,

    Thank you for asking this question. For information regarding connections of EN and PG you can look at Table 5-1. Pin Functions in the data sheet. 

    For EN you can tie it to the input and there are a few connections you can make with PG depending on if you want to monitor Vout. If you do not want to monitor Vout you can leave it floating or tie it to GND. If you do want to monitor Vout then I would suggest pulling PG up with an external resistor to a stable voltage source. 

    To get a 12 V output you should follow the formula attached below. I got the ratio to be R1=17.46R2. Please let me know if you have any further questions regarding this. 

      where Vfb = 0.65 V 

    I would also use this formula to ensure that this is accurate. IFB is around 10 nA so you should probably get something around like 

    R1+R2 <= 12 Mohm -> Which this shouldn't be an issue. 

    Please let me know if you have further questions and I would be happy to assist you. 

    Thank you,

    Josh Nachassi 

  • Hi Josh,

    Thank you for your patient reply. It would be better if there is a complete application schematic.


  • Hi Guohai Lin,

    Hope you had a great weekend. Thank you for this feedback. I will let the team know! 

    Thank you,

    Josh Nachassi

  • Hi Guahai Lin,

    Here is a visual explanation to what I explained in words. I am tying EN and IN together and I am pulling PG pin up to an external voltage with a resistor that is valued from 10k - 100k ohms.

    Hope this helps,

    Josh Nachassi