Other Parts Discussed in Thread: UCC21750
I would like to ask a question about UCC21750Q1:
In our application, UCC21750 is used to drive SiC FET. We used the Desat function and configured the circuit as shown below, we have also done a lot of verification but we currently facing a serious problem:
the Fault signal (FLT) of UCC21750 will be pulled down to low unexpectedly and will be latched unless a reset signal is received from RST/EN ,but at the same time, we also tested the Desat signal, Vdesat, but surprisingly, Vdesat was always low and there was no sign of being triggered. we cannot understand this phenomenon, which violates the logic defined in the specification.
What is the mechanism by which the FLT of UCC21750 is pulled down? Under what circumstances will FLT signal be actively and pulled down to low ?