This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
The input voltage of the push-pull converter is DC24V ( two 12V batteries). DC24V is output to external devices through a diode to supply power. When the push-pull output Vo (DC350V) passes through the MOSFET(Q1)
and outputs at 20KHZ (with a duty cycle of 30%), there is high-frequency interference when there is no load on 24OUT.
The schematic diagram of the push-pull converter is shown in Figure 1
The schematic diagram of the output Vo of the push-pull converter through MOSFET (Q1) is shown in Figure 2
The schematic diagram of DC24 output through D1 is shown in Figure 3
There is high-frequency interference waveform on 24OUT, as shown in Figure 4
What is the source of this interference? How to eliminate this interference?
Thank you!
Hi,
Can you circle the high frequency area in your Fig 4 to indicate where the high frequency noise is?
Figure 4 shows the waveform of 24OUT (without load), which occurs when Q1 is switched on and off at 20KHZ
Figure 5 shows a brief schematic diagram of the entire system
Figure 5
The VO output is very stable, but there are small ripples。After adding a resistor to the 24OUT output, the waveform is OK. The 24OUT waveform is shown in Figure 6. Why can resistors eliminate this interference? Thank you!
Figure 6
Hi,
Hi,
Where did you add the resistor to the 24VOUT in your circuit?
Where is C35 in your circuit?
C35 in Figure 1
add the resistor to the 24VOUT to eliminate interference on 24V
Hi,
please show how you added the resistor to 24VOUT, between 24VOUT to where?
There is high-frequency interference waveform on 24OUT, as shown in Figure 4,so I try to added the resistor to between 24VOUT and GND
Why does removing C35 affect the voltage waveform of pin 2 (EA+) of UC3525 and add the resistor to the 24VOUT to eliminate interference on 24V?
Hi,
The added resistor on D1 to GND can help D1 keep conducting so the ripple before adding R is likely due to D1 on / off.
C35 is for loop compensation. You need to check OUTA OUTB possible differences before and after removing C35 to see any clue.
When removing C35, there are spikes in voltage at EA+and the VDS waveforms of Q10 and Q13 are chaotic, resulting in stable VO output but low efficiency of the push-pull inverter. Why is this?
Hi,
Please capture the waveform of OUTA and OUTB to check the difference before and after removing C35 to see any clue.
the waveform of OUTA and OUTB(Figure 8)
Figure 8
the VDS waveforms of Q10 and Q13(Figure 9)
Figure 9
Hi,
Please label each waveform and also indicate which one with C35 which one not.
Hi,
Figures 8 and 9 show the waveform without C35
Figure 8 shows the waveforms output by OUTA and OUTB of UC3525, namely the two VGS waveforms of a full bridge MOS transistor
Figure 9 shows the two VDS waveforms of a full bridge MOS transistor
Add C35, along with the VDS waveform on this link e2e.ti.com/.../uc3525a-when-i-used-uc3525-as-a-push-pull-converter-and-adopted-full-bridge-rectification-output-i-encountered-some-problems The waveform of Figure 1
Thank you!
Hi,
Can you copy the waveform to this thread after add C35? The link you mentioned does not show clearly Fig 1.
Figure 11 shows the waveform of a single VDS channel
When the load of a push-pull converter is an inductive load, what is the requirement for the output VO and GND of the push-pull converter to have parallel directional diodes? The reverse diode is not shown in the diagram
thank you
Figure 11
Hi,
If it is an inductive load, you need to anti parallel an diode so allow the inductive current to free wheeling. Without this diode, the inductive current would flow through the transformer winding. Your Q1 has a 20kHz on / off so during the off, the free wheeling loop blocked, so the energy dumped to C58 so voltage is higher when next time Q1 turns on.
When no C35, your converter is not stable, so you won't see the 20kHz ripple from average out from this operation. But as it is not stable, you may see other issues.
So you need to add an anti diode in parallel with your inductive load. Or stop 20kHz on/off on Q1,
Hi,
Thsi ia a perfect answer!
Are there any books, or papers that mention inductive loads (capacitive loads)? Precautions for flyback power supplies, forward power supplies, and push-pull power supplies, such as adding anti parallel an diode , etc. Thank you!
Hi,
There are many literatures on the internet. You can search for how to drive inductive load from a dc power supply, or how to prevent dc power supply damage from driving an inductive load.
Similarly, you can also search for how to use dc power supply to drive an inductive load, etc.
It is basically required to provide a freewheeling path. One basic example is buck converter where you see the freewheeling diode or SR to provide the freewheeling path for the output inductor.
The new project adopts the same push-pull converter circuit, with the target voltage VO outputting DC350V (i.e. only changing the resistance value of R96 in Figure 1 to 1.12K)
At first, the T2 turn ratio of the transformer was 3:3:52, which was particularly inefficient. The VGD waveform was similar to the waveform without C35, resulting in a 70% decrease in overall efficiency. However, changing the transformer turn ratio to 5:5:80 resulted in a VDS waveform that was almost identical to the waveform with C35, and the overall efficiency reached 92%
That is to say, the entire project only improves the efficiency by changing the number of transformer turns. What is the impact of the transformer turn ratio on the efficiency of push-pull converters? The entire process C35 was not removed
Thank you!
Hi,
Your design not stable from your waveform which makes additional power losses. The new transformer has a stable operation so helps reducing power losses to achieve higher efficiency.
Besides, more number control f turns can help reducing core losses which may be another reason.
Hi,
May I ask how to search for unstable factors? What factors cause instability in push-pull converters (which can be stabilized by simply replacing the transformer)?
Hi,
You need to measure the bode plots to find the phase margin. You can search how to design loop compensation for push pull converter and type 2 and type 3 loop compensation to help find what you need to know.
If PWM and ADC from TMS320F28035 are used as push-pull converters, and there is no error amplifier similar to UC3525, does the push-pull output VO still require a compensation circuit? What compensation algorithm is used in the program? Thank you!
Sorry, I couldn't find any articles on loop compensation for push-pull converters. Can you recommend some articles on loop compensation for push-pull converters?
Thank you!
What specific examples are there regarding the application of firmware design?
Currently, we only see this example of TIDM_ BUCKBOOST_ What are the main aspects of loop compensation for BIDIR digital power supplies? Is the frequency of PWM or something else?
Hi,
The firmware you use is with a particular MCU or DSP. You need to talk to the firmware design team to know how they make the feedback loop stable. The same similar compensation for Buck boost can be used.
The below can be referenced for loop compensation. Note the compensation for push pull is similar to a Buck.
HiHong Huang,
New problems encountered after the output voltage of the push-pull converter changed
When the sum of R96 and R97 in Figure 12 decreases from 1K to 820 ohms, while other parameters remain unchanged, the MOS transistors (Q10, Q13, Q14, Q15) will be damaged. Why is this? When the output voltage Vo rises from over 400 volts to over 500 volts, this problem occurs. The load is a resistance of 2K 。The PWM frequency of push-pull is 15K。There will be no problem when the output voltage is low(about below 500V)
May I ask if this is a problem with the transformer or the loop compensation circuit?
Thank you!
Hi,
That change may change Vds and current on MOSFET. You need to measure Vds and current to make sure not violating the MOSFET specs.
Hi,Hong Huang
At present, it is suspected that the transformer parameters are causing excessive MOS transistor current, leading to MOS transistor breakdown. What parameters of the transformer will affect MOS transistor current?
Hi,
Figure 13 shows the waveforms of MOSFETs Vgs and Vds with a loaded (2K resistor) push-pull converter, while the correct waveforms of the two VDS circuits are shown in Figure 14
Figure 13
Figure 14
Figures 13 and 14 are two boards with the same design and circuit parameters. Currently, it is suspected that there is a problem with the transformer of the push-pull boost converter, but it is unclear where the problem lies?
Does the secondary current affect the primary side (when the push-pull MOSFET is not conducting)?
Thank you!
Hi,
yes secondary affect primary through the transformer.
You can swap the transformer to confirm if or not the issue due to the transformer. If confirmed then measure the transformer to see differences.
The transformer has been replaced, but it still cannot be replaced. May I ask which parameters of a transformer have an impact on the transformer?
Thank you!
Hi,
I am not understanding your message. It sounds like you swapped the transformers and you confirmed the transformer is the reason to have the bad operation, right? Then you want to know what transformer parameter can cause that bad operation, right?
Hi,
so you need to compare the difference between transformers. I suspect their turns ratios and leakage different.