Using the TPS564257EVM, I'm seeing large (150mV P-P) spikes with a 262mA load with a 1.05V output (As the EVM is configured, right out of the box). The data sheet shows less than 20mV P-P.
Measurements were made right at the EVM connector with a scope using one of those teeny ground leads Is this the expected behavior?. Please see attached scope captures.
Thanks,
Barry
Hi Lucia,
I measured right across C6 (output cap) and it still looks pretty bad (3.4V, 283 mA load):
For comparison, I looked at a TPS54620EVM. There are no visible spikes here, even measuring at the connector:
Hi Barry,
Could you share what changes did you make in the EVM? I noticed the Vout is changed to 3.4V from 1.05V, what Rfb did you use?
Besides, it will be better if you can share the picture of how the output cap was tested, usually we will use the pigtail method to test, like the photo below. Also, can you try to use 20MHz bandwidth of oscilloscope to test again and see whether the spikes still exist? thanks!
BRs,
Bruce
I used the pigtail method. Attached is a pic of my probe. I changed R4 to 46K and C7 to 39pf.(My original post used the original out-of-the-box values).
I also changed the scope BW to 20 MHz and the spikes went away (pic attached). However, all that proves is that the filter in my scope works.
Hi Barry,
Thanks for your feedback!
(1) Let me clarify why there is spike when using full bandwidth. As you can see from below figure, the inductor has EPC(parallel parasitic capacitance) and the output capacitor has ESL. Applying the fast edge of the switching voltage to the parasitic capacitance generates a large current spike through the capacitor, which in turn generates a large voltage spike across the ESL of the output capacitor (see below Equation). That's the reason why you will see spike as below figure.
(2) As for the reason why TPS54620EVM board don't have the same spike as TPS564257. Actually Idid not test TPS54620, but I suspect it may related with different SW dv/dt, different EPC, and different ESL. As you can see from above equation, If you are using same inductor and output capacitor, it would mainly related with SW dv/dt only. With reduced SW dv/dt, it can help to improve this spike.
(3) I would recommend you can also refer to (+) Understanding and managing buck regulator output ripple - Power management - Technical articles - TI E2E support forums if you are interested about this topic.
Thanks and let us know anything unclear. Hope it helps!
BRs
Lucia
