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BQ76952: BQ76952 the output voltage of PACK+ is limited to around 52V.

Star Xu
Genius 9645 points
Part Number: BQ76952

Hi

The customer design with BQ76952, after the battery voltage of 16 series is higher than 52V, the output voltage of PACK+ is limited to around 52V.

At this time, the boost voltage of CP1 also drops from 11V to less than 1V.

At this time, the boost voltage of CP1 also drops from 11V to less than 1V. The DSG and CHG are externally cut off, as are the connections between PDSG, PCHG and MOS.

Increasing the capacitance to 2.2uF has no change. In normal mode and test mode, after initialization, the voltage of CP1 is still nearly 11V before enabling FET, and drops to less than 1V after enabling FET (when the battery voltage is above 52V).

The schematic as below:

Please help check it.
Thanks
Star
  • 0
    TI__Genius 17480 points

    Hi Star,

    It sounds like the charge pump is being overloaded. Looking at the schematic I don't see anything that would cause this.

    To check if it's a possible board/component failure, can you measure the current draw on the CHG and DSG pins when the FETs are enabled?

    Regards,

    Max Verboncoeur

  • 0 in reply to Maxwell Verboncoeur
    TI__Genius 9645 points

    Hi Maxwell 

    Thanks for your reply.

    The LD and pack pin voltage about 52V.

    The screenshot as below:

    Waiting for your reply.

    Thanks

    Star

  • 0 in reply to Star Xu
    TI__Genius 17480 points

    Hi Star,

    Could you please capture a waveform of the CP1 voltage as well as the DSG and CHG pin voltages on a scope during the FET turn on?

    Regards,

    Max Verboncoeur

  • 0 in reply to Maxwell Verboncoeur
    TI__Genius 9645 points

    Hi Maxwell

    Thanks for your reply.

    CP1 voltage change simulates the change from battery voltage 46V, 52V to 58V 10.8V->4.5V->less than 1V.

    DSG voltage: changes from simulated battery voltage 46V->52V->56V.

    CHG: voltage change from simulated battery voltage 46V->52V->56v.

    Please help check it.

    Thanks

    Star

  • 0 in reply to Star Xu
    TI__Genius 17480 points

    Hi Star,

    I apologize for the miscommunication.

    Could you please capture a single waveform at each BAT level of the CP1 voltage on channel 1, the DSG pin voltage on channel 2, and the CHG pin voltage on channel 3. The waveform should be captured during the FET turn on process and show how the voltage of CP1 drops while the FETs are turning on.

    It looks to me from these waveforms that the DSG/CHG pin voltage is clamped at ~56V. You may want to check if D36 is in breakdown (maybe remove it temporarily) and if D35 is populated and also in breakdown. 

    Regards,

    Max Verboncoeur