TPS51200: Power management forum

yang h

Part Number: TPS51200
Other Parts Discussed in Thread: TINA-TI

Dear experts,

I simulated bode plot of DDR3 design with TINA-TI Average Spice Model (SLUM151), I set the conditions the same as those described in Figure 25（DDR3 Design Example Bode Plot ）in data sheet. However, there was a great difference between the bode plot shown in data sheet and simulation result.

Could you please elaborate on this difference?

Best Regards,

8 months ago

+1 Matt Sunna 8 months ago

TI__Guru* 78543 points

Hi Yang,

Unfortunately, I don't think we have a quick answer for you. This device was developed several years ago, so the people who originally created the simulation model are no longer available to investigate this.

These older threads may be helpful though since they are very similar to your question:

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1170845/tps51200-refout-simulation-model-and-capacitance/4408705

https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/85759/bode-plot-of-tps51200

Best regards,

Matt