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Original question:

LM5123-Q1: Strange behavior of low-side-FET gate

LM5123-Q1: Excessive heat on low side FET at low input voltage - issues with dead time?

FelixK
Prodigy 81 points
Part Number: LM5123-Q1

Dear TI team,

we are currently having issues with a design that uses the LM5123.

We are using the LM5123 as a step-up converter, going from 10-32 V input voltage to 32 V output voltage. We originally had some issues with ringing on the low side FET (see related post), which we were able to mitigate using a snubber. However, another problem has occurred.

 

When providing a low input voltage (e.g. 10 V), we get excessive heat from the low side FET, even with light or no load on the output. This behavior decreases when using higher input voltage.

Our preliminary findings seem to indicate that the LM5123 is violating the dead time for the low side FET, and is actually switching the low side FET on while the high side FET isn’t fully closed yet, thus creating a short between VOut and GND.

As a first measure, we added a gate resistor of 2 Ohms to the low side FET to delay the switching of the FET, but this only slightly improves the situation.

We also tried to change the FETs, we originally used the Nexperia PSMN3R2-40YLD, we also tested the ONSEMI NTMFS5C670NLT1G (which is used in the evaluation board of the LM5123), since we feared out original FET might have a too high of a gate charge. However, this also didn’t improve the situation.

Additionally, we have a snubber (2.2 Ohms, 1.5 nF) in parallel to the FET, to mitigate EMC issues. However, the behavior doesn’t seem to be influenced by the snubber, as it is similar without the snubber.

As I understand, the LM5123 has an adaptive dead-time, which actually measures the voltage of the high side FET before switching on the low side FET. Might that be an issue in our design?

Do you have an explanation for the behavior? Is there anything that could improve the situation?

 

Best regards

Felix

Schematic:

  • 0
    TI__Genius 15755 points

    Hello Felix,
    Thanks for reaching out to us via e2e.

    The gate drivers of the LM5123 are very strong as they have been designed for dual FETs.
    We have realized that it is therefore a bit challenging to use it with fast switching single FETs.

    Due to the adaptive dead-time mechanism it is very important that you use the same external gate resistors (and parallel diodes) for Low side and for High side (symmetric conditions for both drivers).

    You have two options:
    - Slow down the turn-on time of the FETs by inserting gate resistors of up to 5 Ohm. Please do not go much higher than that.
          The parallel diodes that you are showing in your schematic will be helpful to avoid that the turn-off will also get slowed down.
    - Use FETs which are reacting slower. As an example, some customers had good experience with the SFS06R06UGF

    Best regards
    Harry

  • 0 in reply to Harry Hofner
    Prodigy 81 points

    Hello Harry,

    thank you for your quick reply! I have two additional questions regarding the options you mentioned:

    1. Our current schematic / PCB layout doesn't include the option for a gate resistor for the high side FET. Would it still make sense to include a gate resistor for the low side FET only, or would that make the situation worse? As I mentioned, including a gate resistor to the low side FET only seemed to improve the behavior. Could you give some insight how the adaptive dead time works, and what the effect of the gate resistors are in that case?

    2. I can't find a local supplier for the SFS06R06UGF. Do you have other FET types that have proven to work in a singe FET configuration?

    Best regards

    Felix

  • 0 in reply to FelixK
    TI__Genius 15755 points

    Hello Felix,

    1. The adaptive dead time is a break-before-make mechanism.
    The voltage on one driver output pin needs to go down below about 1.5V before the other driver output is allowed to start rising.
    There is also some additional delay before the other output will actually get turned on, so that the resulting overall deadtime will be around 20 ns.
    If a gate resistor is used, our device can only see the voltage on its own pin, but not the voltage on the gate of the FET.

    Using gate resistors will have an impact on the timing. The bigger the gate resistor, the slower the FET will react.
    If you slow down the turn-off time of one FET, but keep the turn-on time of the other FET fast, it will reduce the dead-time.
    Therefore the gate resistors should be used in a symmetric constellation.

    2.You can try the BUK9Y series Logic Level FETs, but no guarantee.

    Best regards
    Harry

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • 0 in reply to Harry Hofner
    Prodigy 81 points

    Hello Harry,

    thank you for the information.

    We did some further tests, and it seems the main issue is a rather large variance in the behavior of the LM5123. After testing several devices and finding inconsistent behavior, we placed different LM5123 on the same PCB to rule out issues with tolerances of the other parts.

    We have one IC where the dead time is fine, some others where it seems to be a bit off, and some where it is massively off.

    This also makes it difficult to adjust the circuit using gate resistors, since a setup that fixes the issue with one device / IC may worsen it on another.

    We also did some tests with our development (A- and B-spample) samples, where we used the XLM5123. None of the 6 devices we tested had a dead time issue (compared to 7 ot of 8 devices using the LM5123).

    We also placed a XLM5123 on a PCB (C-sample) where we had the worst problem with a LM5123, and with the "new" IC the dead time / heat issues were gone.

    Do you have an explanation for this?

    Also we noticed a change in the data sheet from rev A to rev B. While the A revision specifies a minimum and maximum dead time tDHL and tDHL, the B revision doesn't have that info anymore.

    A:

    B:

    Can you give some insight on that? At least the minimum dead time is a value where it is rather important to have assured values, and it is odd that the value has been removed.

    Best regards

    Felix

  • 0 in reply to FelixK
    TI__Genius 15755 points

    Hello Felix,

    I do not have proper information on the "old" samples.
    I have seen test data from the LM5123 where the variance was between 19 ns and 30 ns, but this is only some example data.
    If the tolerance of the LM5123 is causing issues, there is some more fundamental issue, where the working combination is already close to the edge.


    The driver outputs are very strong because this part was designed for Dual FET applications.
    This makes it a bit tricky when you use single FETs, especially when they are fast switching.
    You can use gate resistors, but do not go far above 5 Ohms. 10 Ohms are considered as too high.
    And always remember that you will use the same resistors on both driver outputs. Otherwise you will make the dead-time longer on one transition, but shorter on the other one.
    The diodes in parallel to the gate resistors can help to speed-up the turn-off time.
    You may also experiment with capacitors from the gate driver output to GND. The recommendation would be to place these capacitors in the side of the LM5123.
    In general, the LM5123 can only see what is happening on its pins. It cannot know what is happening after the gate resistor (on the gate of the FET).

    If all these methods of tweaking the timing do not work, please use different (slower) FETs with a bigger gate charge / gate-source capacitance.

    Best regards
    Harry

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • 0 in reply to Harry Hofner
    Prodigy 81 points

    Hello Harry,

    thank you very much!

    As other changes will be difficult in this stage of our project, we will test different FETs to see if the behavior changes. If I read your last post correctly, this is also the desired solution, as our FETs may cause the problem, as other solutions as gate resistors or capacitors are more of a work-around.

    I have a few follow-up questions:

    1. We currently use the Nexperia PSMN3R2-40YLD, which has the following gate characteristics:

    Do you have data from customers or internal data what gate charge works well? I just need a rough number, how much bigger the charge needs to be.

    2. Looking at the BUK9Y series, is there a type that you might suggest? Is there a type that another customer successfully implemented as a single FET?

    3. Just for my understanding, wouldn't a higher gate charge also slow down the discharge of the gate, which in turn would decrease the dead time again? Does the adaptive dead time mitigate this?

    4. I mentioned above the change in the data sheet (rev A->B) regarding the dead time. Is this caused by a change in the silicon, or is this just an update because of new statistical data? Do you have information which date codes this change affects? 

    Thank you again & best regards

    Felix

  • 0 in reply to FelixK
    TI__Mastermind 20510 points

    Hi Felix,

    Unfortunately, Harry is out of office today, so the response on this thread may get delayed a bit.
    I will give you a new update by tomorrow.

    Thanks and best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 81 points

    Hi Niklas, hi Harry,

    could you give me an update if possible?

    Have a nice weekend & best regards

    Felix

  • 0 in reply to FelixK
    TI__Genius 15755 points

    Hello Felix,

    I am sorry for the late reply.
    First of all, the people on this forum can help you with questions on our devices but none of us ia a FET expert.
    We do not have a worldwide overview what customers are doing, and we do not really get any feedback what is working well and what not.

    I can tell from my own experience that two parallel NTMFS5C670NLT1G on our EVM are working fine, but a single one does not.
    When I add 5 Ohm gate resistors it is acceptable.
    The SFS06R06UGF worked better for me, but I agree that it is hard to get over here.

    I have seen customers using the BUK9Y6R0-60E and it seemed to work for them. I do not have any exact details.
    Comparing datasheets is somewhat tricky because of the different conditions that the vendors had used for their measurements.

    The numbers in our datasheet are based on measurements on the tester.
    Numbers in an early preliminary datasheet are based on a small number of devices and the tolerance may be bigger than necessary.

    It is correct that a higher gate charge also slow-down the discharge of the gate.
    As I wrote earlier:
    The adaptive dead-time is a break-before-make mechanism.
    The voltage on one driver output pin needs to go down below about 1.5V before the other driver output is allowed to start rising.
    If the voltage on the driver pin takes longer to fall below the threshold, the dead-time will also become longer.

    This mechanism can only work properly if the gate resistors are not too big. our device can NOT measure what the gate voltage would be on the other side of the gate resistor.
    Therefore, a capacitance directly on the driver pin will be recognized and will have an influence on the resulting dead-time.

    Best regards
    Harry

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).