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LP8764-Q1: Reporting UV and OCP fault

Alex Lee
Prodigy 60 points
Part Number: LP8764-Q1

I am facing UV problem for LP8764-Q1 on system reliability qualification. The fault report as following:

 

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x5a r1

0x91

 

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x5b r1

0x02

 

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x5d r1

0x02

 

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x66 r1

0x01

 

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x69 r1

0x02

 ------------------------------------------------------------------------------------------

The log indicates the fault is caused by Buck3 interrupt with UV event.

mfg-s32g> i2ctransfer -f -y 1 w1@0x20 0x5d r1

0x02

 

Currently, I suspect this should be an OCP event causing Vout drop. Some of question should be clarified below.

  1. How is the definition of UV trigger level? Is this Vout*90%?
  2. OCP fault will be reported if the load current above the limit level for 30us, right? If we do not see this fault, the Vdrop might result from high transeint load or other reason? 

BTW,here is current schematic. Please ignore the Iload information.

  • 0
    TI__Genius 9880 points

    Hi Alex,

    the device expert is going to take a look at this and come back to you later this week.

    regards,

    Niko

  • +1
    TI__Expert 6410 points

    Hi Alex,

    Just to confirm is the PMIC device LP876411B4RQKRQ1 as stated in schematics? Referring to https://www.ti.com/lit/ug/slvucf3/slvucf3.pdf User's guide settings.

    Per schematics phase config is 4x1-ph but LP876411B4 is 4-ph actually, so NVM has been changed:

    1. Trigger level depends on the VOUT setting is it presented in voltage or % of the voltage. Also there is setting for this in NVM.
    2. Yes, either load current gets too high or there is sudden load transient which causes voltage to drop.

    Br, Jari

  • 0 in reply to Jari Niemela13
    Prodigy 60 points

    Hi Jari,

    You mentioned he VOUT setting is it presented in voltage or % of the voltage.

    I did not see the UV Vout setting in NVM, and If I am correct, the trigger level depends on 90%*Vout we set 

    Besides, for the current limit timing, the current shoyuld last more than 30us, and then the PMIC will dectect current limit fault.

    Best regards,

  • 0 in reply to Alex Lee
    TI__Expert 6410 points

    Hi Alex,

    Both OV/UV are selectable.

     

    The setting for OV/UV is dependent on output voltage. Below 1.0V it is voltage based and above 1.0V percentage based.

    Yes, when current limit is hit maximum 30µs is latency time for PMIC to take start action. 

    Br, Jari