[FAQ] TPS6594-Q1: How do I set up the Trigger Watchdog?

This FAQ will cover the situation of how-to setup the Watchdog in trigger mode via I2C writes.

Since this FAQ covers multiple parts, there will be slight differences on the implementations will be noted by [TPS6594 / TPS6593] and [TPS8764]

I2C commands as follows: [Base address]: [Write/Read], [Register address], [Write_Data:Mask]

See the end of the post on example usage

Assumptions: The PMIC(s) has successfully powered up, REGISTER_LOCK is not enabled, I2C2 is enabled by default, and the nRSTOUT pin has released (signifying that the PMIC is in known good state).

At the moment the nRSTOUT pin is released the Watchdog is enabled and is in the Long-Window, in this Long-Window the PMIC will be setup to make the changes. All of these commands will take place on the I2C1 bus.

1. Change the GPIO from the I2C2 SDA to TRIG_WDOG
   1. 0x48: Write 0x32, 0x20:0x1F
2. Write your Window 1 & Window 2 timings
   1. Example of setting maximum Windows 1&2
   2. 0x12: Write 0x03, 0x7F:0x80
   3. 0x12: Write 0x04, 0x7F:0x80
      1. The 0x7F is the maximum allotted time of approximately 70ms, double check the datasheet for timing equations
3. Write the new Long-Window time
   1. Example setting 1 minute window
   2. 0x12: Write 0x05, 0x4D:0x00
   3. Note at this point your Long-window needs to be longer than the currently elapsed time plus the extra time to configure the rest of the WD
4. Set the powerhold bit to leave the Long-Window after the Long-Window time elapses & set TRIG_WD
   1. 0x12: Write 0x06, 0x00:0xF8
5. Enable Watchdog if it isn't on default
   1. 0x12: Write 0x09, 0x40:0xBF
      1. This only enables the WD, if you want the default WD behavior simply write 0xFF to this register 
6. Apply rising edge pulse on GPIO and hold high for Twd_pulse (defined in Datasheet) to exit the long window early and start window 1
7. Continue feeding the watchdog in the manner as described in the datasheet

[Write_Data:Mask]: If we wanted only to write certain fields to the register from the Write_Data we apply the Mask.

The mask allows any 0s in a byte pattern to go through and write to the current register without destroying the previous bit pattern in the register.

Ex. Writes 3 bits to the register pattern

1. Current Register value: 0b1101_0011 [0xD3]
2. Write data: 0b0011_1001 [0x39], Mask: 0b1100_0111 [0xC7]
3. Register after Write: 0b1111_1011 [0xFB]

Considerations:

• Each one of these devices has the option of having a separate I2C bus, I2C2 when the respective GPIOs are placed into their SCL_I2C2 & SDA_I2C2 modes the registers concerning the Watchdog are only accessed through this interface. Most variants of these will have this on default for the Q&A function of the Watchdog
• In a multiple PMIC system, the primary PMIC will be handling the Watchdog functionality
• Refer to your devices User’s Guides and Datasheets for base address and Watchdog address as these differ from Part Number to Part Number
• The feeding of the watch dog does involve level detection, but the response to the event is done by a rising edge, then the WD checks to see if it's high level.
  • If the signal is held high at the Long-Window (To exit) and kept there, there will be no rising edge and will elapse in the window 1 & 2, which WILL NOT be detected as an incorrect feeding of the watchdog, but a WD_TIMEOUT error

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Looking for more help? [FAQ] List of FAQs for TPS6594-Q1, TPS6593-Q1, LP8764-Q1 PMICs