I am using Simcenter Flotherm 2210. Could you please provide a .pdml or .pack file? Please use a format that can be read by Ver.2210.
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I am using Simcenter Flotherm 2210. Could you please provide a .pdml or .pack file? Please use a format that can be read by Ver.2210.
Dear Takayuki,
Let me see what I can do for you. Please give me some time.
Thank you,
Josh Nachassi
Dear Takayuki,
I tried to message our thermal engineer, but he is out of office already for the holidays. I will get back with a response after the holidays.
Thank you,
Josh Nachassi
Hi Takayuki
I've submitted a thermal request. Our typical lead time is 2-3 weeks. I'll let you know when I have an update.
Thanks,
Stephen
Hi Takayuki,
I've sent a message to the thermal engineering team and I'll let you know when I have an update.
Thanks,
Stephen
Hi Takayuki,
We expect to have your model by the end of the week.
Thanks,
Stephen
Thank you for providing the simulation model. We are currently proceeding with verification using the simulation model you provided. In order to confirm operation in our environment, we are trying to confirm the reproducibility of 6.4 Thermal Information Values (page.5) listed in the TPS7A57 data sheet.
Could you please provide the following information to the extent possible?
Regarding the JEDEC standard (2s2p) board.
・ Is the substrate size 76.20 mm x 114.30 mm x 1.6 mm?
・ Is the trace area for all trace layers 74.2 mm², located 1 mm inside from the edge of the substrate?
・ Are the thicknesses of the trace layers 70 μm for the outer layers (layers 1 and 4) and 35 μm for the inner layers (layers 2 and 3)?
・ Are the spacings between the trace layers (between layers 1-2, 2-3, and 3-4) uniform?
・ Could you please provide the trace data for the substrate, or any related information? If that is difficult, could you provide the copper foil percentages for each trace layer?
・ Are the die pad exposed areas solder-connected to the substrate? If vias are present, please provide the via specifications (arrangement (number and pitch), diameter, plating thickness, and connected trace layers, etc.).
・ Was the mounting substrate used for all thermal parameters (RθJA, RθJC(top), RθJB, ψJT, ψJB, RθJC(bot)) measured with the same specifications according to the JEDEC standard (2s2p)?
・ Under what conditions was the thermal parameter RθJC(bot) measured?
Here in the information I have on the JEDEC 2s2p high-k board standard:
Thanks,
Stephen