Hi,
The following thread had a status of "Resolved," so I created a new thread. It has the same content as the last question I posted, but could you please check it?
4) Is your answer of (2) correct that/RESET does not become High even in the state shown below? In this case, after the WDI transition is input, the state is fixed with WDI=Low or High. Can /RESET is High after td has passed as shown in Figure 7-1 Timing Diagram?
5) When considering circuits using FETs, is it necessary to pull down with a resistance of 1kohm?
Best Regards,
Nishie
