UCC3818: Phase margin for current loop

Hello Marzieh, 

Most designers prefer to have a phase margin of 45 deg or higher as a measure of stable operation.  While margins as low as 23 deg are still officially stable, it allows some ringing in the current while recovering from transient events in the input current. But it allows the current loop to correct for errors faster.
If transients happen infrequently or with slow attacks, such ringing may be acceptable or insignificant.  A PFC with smooth changes (if any) in load level or line voltage may work well with lower phase margin. 

On the other hand, a PFC load or a line that continually jumps up and down may introduce significant ringing and possible harmonic distortion to the current waveshape, however, the load changes themselves introduce more distortion than the ringing does, so the low phase margin may be a moot point. 

I don't know why the design example is the way it is.  To improve phase margin, I suggest to lower the zero down from 10kHz to maybe 5kHz or lower.  This keeps the mid-band gain Gea at the required 2.611, but allows the phase to begin increasing at a lower frequency for higher margin at the cross-over.  Keep the pole the same, at 50kHz. 

Regards,
Ulrich