About SPEC VIH > 2.1V is High-level and VIL < 1.1V is Low-level , Why test result : VIH > 1.6V is High-level and VIL < 1.6V is Low-level,no voltage window?
Hello Kao,
Yes, the GPIO considers an input to be logic "1" if >2.1V and logic "0" if <1.1V. So, VIH > 2.1V and VIL < 1.1V, as shown in the datasheet.
Can you please share the test result with the VIH > 1.6V?
Regards,
Jonathan Wong
Hello Jonathan,
Test Results:
ch2=gpioC(input) ch3=gpioD(output), FW is 10k polling "gpioD=gpioC"
use EVM board, V33DIO=3.2V
Why is it different from the specification description?
Regards,
Godwin Kao
Hello Godwin,
Apologies for the delay. TI US had a holiday and we are back in office. I have made a diagram of your test results in English for searchability and to ensure I understand your problem. Please correct me if I am missing anything.
Can you please share your schematic and the load that your gpioC and gpioD is connected to?
The datasheet specifies that the max output sourcing and input sinking current is 4mA. If you are loading or sinking more than 4mA, then the output may be lower than VOH and input may be higher than VIL. There is no internal clamp to limit voltage variance so that may be a cause for your behavior.
Please refer to these E2E posts:
Regards,
Jonathan Wong
We use the EVM board for testing,the model is "UCD3138128OEVM-592 PWR592 REV.E2"
We tested 3 signals with an oscilloscope :
CH2 is Input GPIOC pin.(The scale is 500mV)
CH3 is Output PWM2 pin.The scale is 500mV)
CH4 is V33D pin and external power supply provides "3.0V" voltage.(The scale is 1V)
Hello Godwin,
Apologies for the confusion. The test results that you show are actually within the spec. The datasheet shows that VIH > 2.1V and VIL < 1.1V. However, this is only a guaranteed threshold. The behavior between 1.1V - 2.1V is undefined and can be either logic "1" or logic "0".
The datasheet only guarantees that a VIH > 2.1V must return a logic "1" and a VIL < 1.1V must return a logic "0". So, as long as VIH > 1.1V does NOT return logic "0", then the behavior is in spec.
In your test results, a logic "1" does not occur until >1.34V. This is ok since 1.34V is not <1.1V. Any voltage less than 1.1V is guaranteed to be logic "0".
Vice versa, a logic "0" does not occur until <1.70V. This is ok since 1.70V is not >2.1V. Any voltage greater than 2.1V is guaranteed to be logic "1". This is normal behavior.
Regards,
Jonathan Wong
