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UCC14240-Q1: Input Filter

Part Number: UCC14240-Q1

In the Rev. C datasheet Table 8-1 it says "For extreme input ripple voltage cases, connect a 4.75-ohm filter resistor to power input,  PIN7, and connect a 10-μF ceramic capacitor from analog VIN PIN 6, to power analog GNDP." but right above it in Figure 8-1 and 8-2 it seems to show this resistor going to pin 6. Am I misinterpreting what is being shown? or is it the text that is tripping me up? Rvina and Cvina aren't referenced by name anywhere so it's confusing.

First I want to understand what the difference between pin 6 and 7 are? I assume one powers the chip and one delivers power to the integrated transformer?

Next for the input filter does the 4.75-ohm connect between pin 6 and pin 7 or between Vin and pin 7? Is the 10μF in addition to the one mentioned at the top of this table entry? and should the ground side of it be closer to pin 5 or pin 8 (both seem to be important for different things as per the Vin entry in Table 5-1)? 

And ultimately I want to know what implementing both the optional 330pF and the input filter looks like?

  • Nicholas,

    I copy/pasted each of your questions below. My answers are shown in each bullet item. Adding the optional filters described in Table 8-1 should only be considered when the total input capacitance is lower than expected, or perhaps the pre-regulator output capacitance is low or maybe there is some impedance between the pre-regulator and the UCC14240-Q1 or maybe you have several UCC14240-Q1 devices turning on simultaneously. Any of these conditions can result in transient excursions at VIN or higher than expected voltage ripple on VIN. As we have completed several IC revisions leading up to the release of UCC14240-Q1, the input voltage sensitivity is more robust and I've reviewed hundreds of successful designs not using the input RC filter. However, we decided to leave this description/recommendation in Table 8-1 due to lessons learned from early development versions of the IC.

    "In the Rev. C datasheet Table 8-1 it says "For extreme input ripple voltage cases, connect a 4.75-ohm filter resistor to power input,  PIN7, and connect a 10-μF ceramic capacitor from analog VIN PIN 6, to power analog GNDP." but right above it in Figure 8-1 and 8-2 it seems to show this resistor going to pin 6. Am I misinterpreting what is being shown? or is it the text that is tripping me up? Rvina and Cvina aren't referenced by name anywhere so it's confusing."

    • Yes, it is confusing and ambiguous. I will work internally to clarify what needs to be communicated. Below is what each of the options described in Table 8-1 should look like when placed into a schematic

    "First I want to understand what the difference between pin 6 and 7 are? I assume one powers the chip and one delivers power to the integrated transformer?"

    • Both are VIN and are typically connected together on the PCB externally. Internally, pin 6 is bonded to analog input voltage sensing circuitry while pin 7 is bonded to the power stage.

    "Next for the input filter does the 4.75-ohm connect between pin 6 and pin 7 or between Vin and pin 7?"

    • Connect the 4.75Ω resistor between pins 6 and 7 as shown in the schematic diagram above

    "Is the 10μF in addition to the one mentioned at the top of this table entry?"

    • Correct and referring to the schematic above, this would be C16 in addition to C12

    "and should the ground side of it be closer to pin 5 or pin 8 (both seem to be important for different things as per the Vin entry in Table 5-1)?"

    • GND side of the 10μF filter capacitor (C16) is connected directly to pin 5. Pins 8,9 are the GNDP pins for power (also heatsinking) and should make direct connections to C12, C13. Pins 10-18 are used primarily for heat sinking

    "And ultimately I want to know what implementing both the optional 330pF and the input filter looks like?"

    • See option 1 in schematic above. In the worst case you could implement option 1 and option 2 together but since they are described as separate options in Table 8-1, I am showing them schematically as separate options.

    Regards,

    Steve