UCC2818: OVP/EN circuit

Hello Nishie-san, 

I looked at the previous E2E thread that you reference and I think I understand the issue. 
Actually, I was unaware of this problem with the UCC2818 and I believe it is the same as your customer issue that we discussed by email last week.
Thank you for bringing it to my attention.  

The full quote is this: "Finally the problem was fixed. The OVP/EN pin enabled the PFC before VCC turn-on threshold was reached. Adding a circuit to delay when OVP/EN goes high sorted [solved] the problem. "

I do not know what the delay circuit is that solved the problem, but I think I can recreate it here: 
Since the 7.5V VREF output is held to 0V until VCC rises above its UVLO turn-on threshold, VREF can be used to delay a signal to OVP/EN pin.
1. Connect a small-signal NPN collector to OVP/EN, emitter to GND, base to 100k resistor to VCC. 
2. Connect a second NPN collector to base of first NPN.  to the gate and R-C junction of the first MOSFET, source to GND. 
3. Connect the base of second NPN through a 100k resistor to VREF.  Also connect a 1uF cap from second base to GND.

Before VCC reaches UVLO, VREF is low so second NPN is off.  First MOSFET is on and keeps OVP/EN tied to GND.
When VCC reaches UVLO, VREF turns on and starts charging the cap on the base of second NPN.  Once Vbe = 0.7V, the second NPN turns off the first NPN and OVP/EN is released.  Time delay from 100K and 1uF on second NPN base can be adjusted longer or shorter, as needed.

I hope this works for your start-up rise time problem from your previous E2E. 

Regards,
Ulrich