LM25119: Design is not able to regulate properly under load.

Hi Brian,

The circuit is detecting an over current. This is why it is in hiccup mode. 

1- Check the inductor saturation current 

2- Increase the RC filter 10 to 20 times

Regards

For 1: Inductor vendor datasheet is listed that the Isat is within specification or the design requirement

For2: 10R-1nF-10R is adjusted to 100R-1nF-100R and voltage drop is occur

100R-10nF-100R also having same voltage drop

Hello,

Do you mean with higher filter the result is better?

Regards

Negative, both configuration is the same and show no different.

Meantime, I had assemble another version of PCB with different bulk cap but the result is the same with voltage drop once there is a CC load.

answered offline

Hi Mahmoud,

The UVLO is adjusted according to the suggestion of lower down the input voltage and due to layout parasitic Cdv/dt.

Previous UVLO configuration resistor network is based on the QuickStart spreadsheet, and with a VHYS of 2V the suggested value is:

100k, 8k47. On the board the value is selected 100k, 8k87.

With a new UVLO, I tried to reduce the VHYS to 1.36V and 6.91V shutdown voltage.

The suggested value is 68k, 15k02, which 68k and 15k is placed onto the board.

With the above modification, the converter is unable to run near 8V but once it is above 9V.

Converter can regulate strong and stably.

Please TI explain why and do the VHYS current enters the UVLO pin is insufficient and result in an unstable regulation?

As for more buck converter question I am going to cont'd offline.

Bests,

Brian

Hello, the tolerances should be considered when calculating the UVLO

Regards

Hi Mahmoud,

This is not answering the question nor resolving the previous issue:

From the QuickStart spreadsheet the hysteresis is designed by user and with the above setup the converter will result in a non-regulatable converter.

But once the VHYS is reduce the converter is working properly.

Please explain and resolve the situation. 

Hello,

what do you mean by VHYS reduce? how is the input supply looks like? Can you send a scope picture for VIN and UVLO signals?

Regards

Ok let me repeat the case from beginning and refresh all the memory:

At the very beginning after the design review. The first revision is printed and assembled.

After assembled and test the converter is unable to reach the targeted output voltage.

Here we are talking about revision 1.0.0.

Suggest is made and looks like the hiccup mode is happened and output capacitor might be reversed in polarity.

After checking indeed 1 out of 6 capacitors are reversed and replaced and yet no valid regulation is given.

With further review, a suggestion is given on the analog around fix:

Here we are talking about revision 1.0.1

After analog ground is modified, the reprinted board is unable to reach targeted output voltage.

A new suggest is made to increase the current sense filter value.

Converter is able to reach targeted output voltage when no load is applied.

However once the converter is applied with constant current load at 0.5A the voltage drop significantly.

Another revision is printed with output capacitor modified and the component placement is placed more easy to manually reassemble.

Here we are talking about revision 1.0.2

With all the modification the board is repeating revision 1.0.1 situation and no different is made.

Converter is unable to regulate during constant current load is applied.

A new suggest is made on the large switching node copper pour.

Your theory suggest a large Cdv/dt could introduce fake current spike and introducing over current sensing. 

Based on such you suggest reducing the input voltage from targeted 26V to 8V.

With such simplified suggestion and "NO" modification guide:

I used my understanding of LM25119 that reducing the input also require adjusting the UVLO accordingly.

I tested the board revision 1.0.2 with a new UVLO resistor network.

Such resistors are based on Quick-Start spreadsheet and hysteresis voltage is reduced from 2 to 1.3V.

Before UVLO modification all three revision board is using the same UVLO resistor value 100k and 6k8 as UVLO is set to ~18V.

And three revision board is unable to regulate and deal with constant current loading.

Once the UVLO is adjusted to work with 8V input range.

The converter can regulate and run on heavy constant current load.

All the output waveforms are normal and no hiccup is shown.

"SO ABOVE HISTORY TELLING ME THAT the CONVERTER IS NOT WORKING PROPERLY DUE TO >UVLO< SETTING"

PLEASE TI explain why this is the case and do the UVLO resistor is faulty or there is s.t. missing the in Quick-Start Spreadsheet?

Bests,

Brian

On top of the long reminding of this ticket.

I have tried to repeat the configuration on previous revision 1.0.1 board and instead of layout.

Both 1.0.1 and 1.0.2 components are aligned and shared the same values.

And result of both 1.0.1 and 1.0.2 can regulate with no issue.

So it is a must that the UVLO is doing the job but no explanation.

I urge TI to give out more explan and allow user to have a better control on LM25119 product.

Hello,

I understood that you changed the UVLO level and the hysteresis to start at 8V. At 8V the regulation is OK. How about higher level? if you rise the input voltage to 24V, is still regulate with load? 

Regards 

NO NO NO NO NO

Please read!!!!!

I had said many many many times.

The converter is NOT working properly at 8V but 23V to 30V.

Could you read before reply.

I had repeated this many many many times!

Mahmoud,

The issue is not related to the supply voltage but why adjusting the UVLO make such different.

Am i making myself clear?

The UVLO resistor is based on the Quick-Start spreadsheet and there are no RED color or any indication that the VHYS is design inappropriate.

So I need some explain and guide to avoid or cope with such puzzling behavior.

Sir,

I'm sorry to say you are writing a lot but you still not answering my questions. It is simple:

1- The UVLO circuit is not related to regulation

2- QuickStart file is not 100% optimized to make the circuit work

3- UVLO parameters should be considered

4- It seems your problem is due to supply voltage fluctuation and is entering the UVLO region

Is your circuit working or not?

Regards

I write a lot not because I want to but sound like you are in AM and I am in FM two complete two type of signal that is not decodable from each other.

1) When you are pointing out the UVLO is not related to proper regulation the experiments on board R1.0.1 and R1.0.2 shows that is not the case.

2) This is understand which is why I am pointing out the possible hazard here.

3) But what parameter I only got a simple modify the input to 8V and try guidance 

4) If this is the case are you suggesting the current with high hysteresis will result in insufficient current that make the signal pin of UVLO very sensitive?

The circuit is working on 26-30V and 0-30A but this is not explained why this is working and before is NOT.

The only different is the UVLO resistor network. 

With the value is selected 100k and 8k87, the circuit should be working around 17V. I double checked the schematic and there is no filtering capacitor at UVLO pin. Can you please add 220pF in parallel to R4. I think the converter is shutting down due to noise at UVLO pin. When you set the voltage at around 8V, the noise does not affect it because the input voltage is 26-30V.

Regards

According to the EVM indeed there is a 100pF capacitor is coupled.

So this is suggesting that the UVLO is very subjective to noise as the current is not strong enough against the surrounding noise spectrum?

Please comment that the PCB layout is having a very close coupling capacitor on the VIN power line and very close to the voltage divider of the UVLO network.

Are you suggesting that even with a coupling capacitor on the VIN pin before passing the voltage divider of UVLO is still not enough to settle the noise coupling to the converter?

Or due to high resistance divider is used the charge on the UVLO pin is insufficient and that's why a pF range capacitor can hold the charge and reduce the noise coupling?

Bests

On top of the last response. Now I can see the full picture more clearly.

First DATASHEET LM25119, Section 8.2.1.2.12 UVLO Divider.

Do explain a Cft is needed but not labeled as a must.

Second Quick-Start spreadsheet schematic is missing such Cft and no value is given in any cell.

And appropriate Cft value such as 220pF that you are suggesting is not given or calculated.

Third, before such UVLO adjustment coincident is happened, I do probed the UVLO pin and no sign or noise nor spike is found.

So I am still not understanding what is triggering the converter not working properly from beginning?

Bests

Sir,

please go ahead and add the filtering capacitor on UVLO pin.

Regards

Yes, I do added the capacitor 100pF // with 8k87 and replaced back to 100k& 8k87.

The converter is performing same as adjusted UVLO 68k,5k, which is regulated properly.

So this also explain the converter is having trouble on high resistance resistor network.

Bests

Hello,

If you think your problem is resolved and the circuit is working, please close this thread.

Regards

I don't think the problem is considered as settled.

There are no clear explanations why adding pF range of capacitor will resolve the issue.

While even when 68k and 5k have no filter capacitor and converter could regulate properly.

This is not a proper way nor method to fix the circuit.

Please give more elaboration why is the case on UVLO is having such issue.

And datasheet and Quick-Start guide is not giving design constrains on such requirement.

I think you mean 68K and 15K and not 5K. 

- 68K and 15K, UVLO = 4.15V at VIN of 23V. This UVLO is much higher than the 1.25V threshold and not affected much by the noise

- 100K and 8.87K, UVLO = 1.87V at VIN of 23V. This UVLO is close to 1.25V threshold and sensitive to noise

The Quick-Start does not consider noise.

I hope your questions are answered. 

Regards