TPS65988: GPIO #12 not Acting as "Port 0 Source PDO Negotiated TT 1" Not asserted for 9V or 20V PDOs- Stays low

Hi David,

Port A is port 0 on both. PortB should be port 1.

Could you share a table of what you are seeing on the GPIOs for different voltages negotiated?

You project only has 3 source PDOs, 5, 15, and 20. Is this correct.

My understanding is the TT positions are binary encoded, and correspond to the PDO, so the missing 9-V pdo means the GPIOs will be mapped differently than the table you posted.

Your project settings in the GPIO register look correct for the two events. Is there anything connected to the hardware that could be driving the GPIO12 pin low?

Could you also try using the "project, import settings from project" feature to transfer the DK project to a DH project and see if that has different results?

Thanks and Regards,

Chris

Hi Chris,

Here is the circuit and table.  PDO_0 is only connected to GPIO12;  PDO_1 is only connected to GPIO13.

GPIO12 stays low regardless of what volteage is negotiated.  We have gone through a lot in getting our system to work. Our system can use a wide range of power and gets additional features when more power is available.  It is a PC peripheral.  It can work by only  connecting port A to a PC.  Port B is for power only.  When using port B for power, after calculating the power required by the peripheral, remaining power is sourced to the PC.  We were hoping to be able to save on BOM costs by using the internal switch to sink on Port B while following the EVM and  sink with external swithes and source with the internal switch on Port A.  We were not able to get the sinking to work properly this way- we damaged anumber of TPS65988 parts in this process.  Thankfully we put option resistors and external switches on Port B just in case.  

We are now able to get all the sinking working properly, we are now only having problems with sourcing on Port A.  There are a few wierd things that are happening with our system.  If I have source 4 source PDOs for 5, 9, 15 and 20V, only 5, 9 ,and 15 are offered.  If I remove the 9V PDO, then 5, 15 and 20 are offered. This why the .pjt file that I sent only has 5, 15 and 20V.  

I wonder if you were to send me the default .pjt file for a TPS65988 based EVM and I started working on this from that point if I could get things to work.

Either that or you could make me  a .pjt file for what I need :-)

We need  the following:

• sink up to 3A on both ports and up to 5 V on Port A and up to 20V on Port B.
• seemlessly switch sinking from Port A (connect to PC- peripheral powers up and communicates with PC) to Port B (sinks from Port B rather than Port A and continues to communicate with PC on Port A).  Disconnecting POrt B at this time causes the peripheral to reset, which is OK
• Source up to 3A on Port A.

After powering up, we Clear the dead battery flag.  When we know that power is being sourced from Port B we calculate left over power, adjust the Port A source PDOs then issue PRSWAP command on Port A.

Thanks,

David

Hi Chris,

Thanks!  I will have time to work on this again next week. I will update the thread at that time with how it goes.

Hi David,

Sounds good, awaiting updates.

Thanks and Regards,

Chris

Here are my results:

Default TPS65988DH, Advanced, DFP only project 

I added sink PDOs (there are 0 in this project template)

Connecting to the laptop on Port A, power is negotiated properly, (5V 3A is offered and accepted) but PP3 is not asserted and the 5V is not switched to the SYS power.

Default DRP prefers power source

Changes include:

- 0x29 Externally powered disabled; Initiate Swap to Source Disabled

- 0x27 Only highest power port closes switch

Connect laptop to Port A: power is properly negotiated and connected to SYS

Connect charger to Port B: 20V power is negotiated, not switched to SYS

Port A Deadbattery flag cleared:    SYS switched to Port B source (20V)

Port A Swap to Source command: 

Accepted by PC, 5, 9, 15 20V PDOs offered to PC, 20V requested, only 15V provided.  Hard reset occurs as a result.

This is slightly improved over what I was seeing with the original .pft in this thread, except that this is offering all 4 source PDOs. GPIO12 is not being asserted where it shouild and as a result only 15V is put on VBUS.

Default DRP prefers data host

Changes include:

- 0x29 Externally powered disabled; Initiate Swap to Source Disabled

- 0x27 Only highest power port closes switch

- 9, 15, 20V sorce PDOs added

- 0x5c GPIO 12 mapped to Port 0 Source Negotiated TT1; GPIO13  mapped to Port 0 Source Negotiated TT2

The result is identical to Default DRP prefers power source, except, only 5V is sourced, so neither GPIO 12 or 13 is asserted.

Is there something that I am missing? Is there a way to get GPIO12 working properly with the Default DRP prefers power source template?  

TPS65981_2_7_8 Application Customization Tool GUI Version : 6.1.4 has added support for TPS65987D/88 DK.  Is it possible that this broke things when used with the TPS65989DH?  Can I get version  6.1.3? 

Best regards,

David

Hi David,

I am doing testing with a 988DHEVMin parallel, and have not seen any issues with GPIO12 asserting. I am using GUI version 6.1.4 and have not seen any issues.

To make sure we are on the same page, to generate the new project in the 6.1.4 GUI, here are the steps I followed.

1. Project -> New Project
2. TPS65998DH
3. Advanced
4. DFP Only

Here is the pjt file I generated using these steps

Default_DRP.pjt

I also generated this project from the DFP project with added sink contracts, and I am able to power port B with a wall adapter, send the DBFG command, and negotiate and source 5, 9, 15, and 20-V contracts on Port A.

Edited_DRP_with_Sink_988EVM.pjt

Can you share your latest pjt you generated so I can test it with the EVM? Can you also remind me which power paths you are using for which roles(source/sink)? I remember your hardware had them configured differently than the EVM?

Could you test setting GPIO 12 to the OUTPUT enabled without event and see if GPIO12 even goes high? See the image below for the GPIO configuration. Make sure initial value is set to 1.re?

Have you tested the same pjt on different pieces of hardware? Is there anything that could be pulling the gpio12 low or preventing continuity from the PD controller to where you are measuring?

Thanks and Regards,

Chris

Thanks for all this Chis.

Here is our power block diagram.  For a long time we were trying to sink using internal switches on Port B and external switches on Port A, but kept running into problems.  So not we are doing everything the same as on the EVM with default jumpers (sink using external switches on both ports and source using the internal switch on Port A) except that the internal Switch on Port B is not used.

Should the firmware base image be TPS65987_88_F707_10_10.bin? TPS65987_88_F907_14_14.bin looks like a later version.

Here is the latest .pjt that I created based on the DRP power source defaults.

 DRP_Pwr_Src1.pjt

I loaded Edited_DRP_with_Sink_988EVM.pjt to my system 

connected Port B to a wall charger:  SYS = 20V

DBFg command

connected Port A to laptop.

Protocol analyser shows that the port did a sink negotiation from the laptop.  SYS continues to be powered by the 20V from port B but, Port A is also negotiated as a sink but at 5V.  

Port A SWSr does nothing.  In previous experimentation, I believe that I needed to set Process Swap to Source in order for this to work.

Last night I also uninstalled the configuration tool and re-installed.  Just in case something got funky.

Our system is only powered by USB-C and has no battery.

In debug mode I executed this command and was able to verify that GPIO 12 goes high: