UCC2818A-Q1: Voltage Error Amplifier

Hello Aravind, 

In the example shown, Gva is the closed-loop gain of the voltage error-amplifier at the frequency of the PFC output ripple voltage. 
That ripple voltage is indicated as 3.91V zero-to-peak, and that ripple frequency is twice the AC line frequency.

In the section preceding the Gva discussion, it was shown (by SEM-700 Topic 7) that allocating1.5% of the VFF ripple contributes to half of 3% THDi from the 3rd harmonic of the line.  Similarly, 1.5% of the VA output ripple contributes the other half.  So the EA gain necessary to attenuate this ripple (divided down from Vout) is: 

1.5% of VAout(max) (= 5V) /  (2*3.91V) =  0.0096 = Gva at 100Hz (or 120Hz) 
This value of Gva is used in the follow-on equation to calculate Cf. 

Since the UCC2818A-Q1 has a voltage feedforward function, VAOUT is not influenced by input voltage, so its amplitude is basically proportional to output power. 
If 5V corresponds to maximum power (250W), then VAOUT = (35W/250W)*5V = 0.7V corresponds to 35W (14% of full load). 
VAOUT voltage for other loading is estimated the same way. 

Regards,
Ulrich

Hello Aravind, 

To better understand the UCC2818A-Q1 error-amplifier relationship to output power (and by extension, to input power) please review this application note concerning the UC3854, particularly around page 3-281.  https://www.ti.com/lit/pdf/slua144 
It is written for an older PFC controller, but its operating principles form the basis for the UCC2818A-Q1, and the app-note discussion on multiplier operation (including the error-amp) still applies.  

For variable input frequency operation, it is best to design for 800Hz.  Strictly speaking, it is impossible to ensure that "performance should not deviate" between 350Hz and 800Hz; it will deviate.  However, you can expect that performance should be better at 350Hz, so 800Hz is the correct design target.

Regards,
Ulrich

Hi Aravind, 

The decision that a single-pole filter was adequate for a 50Hz design was made by the author of the design example.  A two-pole filter can have lower ripple voltage but is more complicated to design (see design guides for UC3854 controller https://www.ti.com/lit/pdf/slua144 pages 3-284, 3-285). 

The assessment of adequacy depends on how much ripple attenuation you think you might require to meet THDi targets.
But a filter good for 50Hz is also good for 60Hz.  

Similarly, a 1- (or 2-) pole filter on VFF for 350Hz will be good for all higher frequencies, certainly to 800Hz. 

Regards,
Ulrich

Hi Aravind, 

The requirement for <1.25% THDi over a light to full load range is extremely stringent.  I don't know if it is even possible. I suppose it could be possible if enough technology is designed in to overcome the sources of distortion, but I think it will be very complex and very costly and time consuming.  
I will not be able to help you achieve this goal. 

PF is a combination of phase-shift and harmonic content of the input current with respect to that of the input voltage. 
Please see this paper on the topic:  4812.PF_THD_Power.pdf

Most of the phase shift comes from reactive current in the line-filter X-caps, the magnitude of which depends on their total impedance at the input frequency. 
The harmonic content comes from distortions introduced by the controller, mostly from ripple voltage on the error amp output and ripple on the VFF node.
Those two signals are inputs to the multiplier whose output forms the reference signal for shaping the input current.   
The design guide that I referenced previously discusses how to minimize them, although the paper considered 3%THDi to be adequate. 
You will need to modify the design targets so that they both contribute < 1% THD combined, in my estimation.  

The remaining THD comes from current-sense offsets, propagation delays, and other factors which I have no experience about.  
I have reached the limit of my ability to help you. 

Regards,
Ulrich

Hi Aravind, 

For the VFF ripple attenuation to minimize distortion, you should design for 350Hz, which will also work for 800Hz as I mentioned earlier.  

When I said " it is best to design for 800Hz. " two days ago, I meant in reference to the error-amp gain needed to attenuate error-amp output ripple.
Also, the choice of switching frequency should be based on the 800Hz end of the operating range. 

It is apparent that different aspects of the PFC design require optimization at different ends of the input frequency range. 
I apologize for making that blanket statement without qualifying under which conditions it applies.   

In general, all corners of a design (high line, low line, high load, low load, high freq, low freq, high temperature, low temp, etc., etc.) must be considered while trying to meet all of your design requirements. 

Regards,
Ulrich

Hello Aravind, 

Your calculation for Rff and Cff should follow the design method in the UCC2818A-Q1 datasheet.  I'm not sure how design a 2-pole VFF filter on this device.

Your simulation is of a voltage source driving a series R-C filter.  It is not valid for UCC2818A-Q1.
The actual VFF circuit in this device is a current source driving a parallel R-C filter.   Please read the datasheet on this topic. 

The VFF circuit contributes only about half of the total THDi.  The ripple on the error amplifier output (VAOUT) contributes about another half.  The remaining THD comes from offsets and other non-linearities in the system.     

In any case, I cannot predict or guarantee any specific amount of real-world THDi from a simulation model.  No model is detailed enough to include every possible non-linearity that may occur in a circuit.  You simply have to build a prototype and measure it. 
The simulation can give you a gross idea of the 3rd harmonic THD based on the ripples on VAOUT and VFF.  This may be most of it (THD), but not all of it.  

Regards,
Ulrich