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Good morning,
I have a query on TPS7A57 as follows.
The transient response of the LDO is shown in datasheet image 6.33-6.36.
I notice that there is no ringing in the output for the load transient and the peak to peak ripple is also very low.
In typical discrete LDO circuits (Say a TL431 based or Opamp based), there is a pole placement using a capacitor for zero steady state error, that may result in higher overshoots and larger oscillations.
Where as in the LDO IC, the block diagram does not show any presence of such capacitance. In such a condition, how are we able to achieve zero steady state error? Is the LDO operated in hysteretic mode control internally with the opamp in open loop? Or are do we only use a proportional based control internally for lowering the transient ripple specifications? Where exactly is the compensation network for the LDO?
Any clarification in this regard is appreciated.
Warm regards,
Siri
