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Original question:

BQ76952: BQ76952 top-cell balancing current less than other cells

BQ76972: Balancing duty cycle for top cell is much lower than for other cells

Vasily Shmatalyuk
Prodigy 150 points
Part Number: BQ76972

Tool/software:

Greetings,

I'm using BQ76972 for a 4S smart battery design. The bottom three battery cells are connected between VC1 and VC0, VC2 and VC1, VC3 and VC2, respectively, while the top cell is connected between VC16/15 with VC15-4 shorted. Testing the cell balancing capabilities of the chip I observed that the balancing duty cycle is much lower for the top cell compared to the bottom three: ~36% for top cell and ~91% for the bottom three. See scope shots below:

 

Some context:

- Only host-controlled balancing is used (through 0x0083 CB_ACTIVE_CELLS()), automatic balancing is disabled

- Balancing resistors for all cells are 20-Ohm

- CB_LOOP_SLOW1/2 and LOOP_SLOW1/2 are disabled, ADC runs at 63ms

Question:

Is this reduction of top cell balancing duty cycle expected? If yes, what are the options to alleviate it?

This behavior produces a drastically reduced effective balancing current for the top cell, which is quite confusing. I see several other forum posts mentioning similar symptoms, but nowhere does TI explicitly acknowledge that behavior is expected. Section 10.2 of BQ76972 TRM mentions the reduced effective balancing current due to measurements but doesn't explicitly mention unequal duty cycle among cells.

-  BQ76952: BQ76952 top-cell balancing current less than other cells 

-  BQ76942: Cell 8 and 9 on top of battery pack balance much slowly 

-  BQ76952: Current consumption during balancing process 

Thank you in advance,

Vasily

  • +1
    TI__Intellectual 1440 points

    Hello Vasily,

    This issue has to deal with the configuration of the CB_SLOW_LOOP. To increase the average current on the top cell when balancing, the CB_SLOW_LOOP must be properly configured.

    For more details on the reasoning and method to configuring the CB_SLOW_LOOP please refer to this thread here.

    Regards,
    Rohin Nair

  • 0 in reply to Rohin Nair
    Prodigy 150 points

    Hi Rohin,

    Thank you for getting back to me so quickly. Having the battery monitor reduce its sample rate at balancing is pretty suboptimal for my application, but at least your insight that reported behavior is expected de-risks my hardware design.

    Perhaps you can help me with another question. Since the top cell is connected to VC15-14, I suspect it is expected that its readings are reported as cell16. Thus in order to read synchronous voltage/current measurements for all 4 cells, I have to use two rather then one expensive subcommands: DASTATUS1 (0x0071) for bottom three cells and DASTATUS4 (0x0074) for the top cell reported as cell16.

    Question: Can you confirm that following TI HW design recommendations connecting the top battery cell to VC16/15 and shorting unused cell input pins results in the necessity to read top cell voltage as cell16 rather than cell 4 in my case? If so, is there any way to make the top cell (cell 4) map to cell 4 as reported by BQ76972?

    I appreciate your support.

    Kind regards,
    Vasily

  • 0 in reply to Vasily Shmatalyuk
    TI__Intellectual 1440 points

    Hello Vasily,

    Yes, I can confirm that connecting the top battery cell to VC16/15 is recommended which will in turn require you to read top cell voltage as cell 16 rather than cell 4. However, if cell balancing is not a necessity for your application, then you are not required to connect your cell 4 to VC16/15. If cell balancing is required, then unfortunately the two subcommands will be required to read synchronous voltage/current measurements.

    Regards,
    Rohin Nair

  • 0 in reply to Rohin Nair
    Prodigy 150 points

    Thank you Rohin, copy that. I appreciate your quick support.