LM5143A-Q1: Current Imbalance Observed in LM5143A-Q1 4-Phase Synchronous Buck

Hello Yuming

Could you please share your PCB layout file for review? As per my understanding schematic design is same as we discussed over  (+) LM5143A-Q1: Technical Questions Regarding LM5143A-Q1 2-Phase / 4-Phase Synchronous Buck Operation - Power management forum - Power management - TI E2E support forums

Thank you 

Regards

Onkar Bhakare

Hi Onkar:

Thank you for your reply. We believe we have identified the root cause of the issue. It appears that the inductor used in Phase 2 is slightly different from the others. When we swap the Phase 2 inductor with one from another phase, the MOSFETs in the swapped phase show higher temperatures. This indicates that inductor variation is likely contributing to the current imbalance among the phases.

We would also like to share part of our PCB layout for your review. The design is based on a 4-layer PCB, with all components placed on the TOP layer. The 50 V input (Vin) is routed on Layer 2. For thermal management, the PCB is mounted to an aluminum enclosure with thermal paste to aid heat dissipation.

During testing at an ambient temperature of 24 °C and Vin = 50 V, the maximum load current we can achieve is 48 A. At this operating point, the MOSFET case temperature reaches approximately 135 °C.

Could you please advise on what modifications or improvements—such as PCB layout optimization, thermal management enhancements, or MOSFET selection—would be necessary to achieve 70 A load current at Vin = 50 V?

Thank you 

Regards

YUMING

Hello Yuming

After inserting FET parameter in the QuickStart estimated efficiency looks quite poor.

here are some suggestions on optimization

1. Reduce Rg to 1 Ohm or lower
2. Bottom FET with lower Rds on could be chosen or two FETs can be connected in parallel
3. Switching frequency can be reduced, however output filter and compensation will need modification accordingly  

Thank you

Regards

Onkar Bhakare

Hi Onkar:

We are currently using the ISC0805NLS MOSFETs, and the calculated efficiency is shown in the figure below. At present, the gate resistors for the high-side MOSFETs have been adjusted to 3.65 Ω and 0 Ω, while for the low-side MOSFETs, both gate resistors have been set to 0 Ω.

Our design target is to achieve 15 V / 70 A output with Vin = 50 V. However, in our current testing at ambient 24 °C, we can only reach a maximum of 48 A load, at which point the MOSFET case temperature rises to about 135 °C.

We would like to ask for your support in reviewing our PCB layout. Could you please advise if there are any areas where the layout should be improved to help optimize thermal performance and enable us to reach the 70 A load target?

Regards

YUMING

Hi Onkar:

Thank you for your suggestions. We will discuss them internally. You may close this topic for now. Thanks.

Best regards,

YUMING