D-CAP explained

This app note explains the tradeoffs between current and voltage mode control

http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=slua119

I don't know of an app note explaining the differences between the flavors of D-CAP mode.  But by reading the descriptions from different datasheets, we can note some differences.  Always refer to each device's datasheet for an explanation of how that particular device is designed and meant to be used.

From the TPS53126 (D-CAP2): does not require ripple on the output for regulation

"The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP mode control."

From the TPS51218 (D-CAP): requires output ripple to regulate

From the TPS51727 (D-CAP+): output voltage set by VID

"The TPS51727 is a DCAP+™ mode adaptive on-time converter. The output voltage is set using the 5-bit VID code defined in Table 3. "VID-on-the-fly" transitions are supported with the slew rate controlled by a single resistor on the ISLEW pin."

Note that you posted to the external forum.

Actually, you can make gain loop response measurements with DCA2.  Since DCAP2 uses adaptive on time and pseudo-fixed frequency, the switching waveform is is relatively uniform.  TPS54327 is not exactly DCAP2 as there is no eternal VO pin, but you can measure the loop in the usual manner by injecting into the feedback loop.  You do need to be careful about interpreting the results however.  The TPS54327 will show a high crossover frequency and depending on the output voltage, may hve less than 45 degrees of phase margin.  It is inherently stable, as the phase is increasing at crossover rather than decreasing, so there is no danger of oscillation.

That equation you reference is applicable to DCAP, not DCAP2.  DCAP 2 uses internal ripple injection to allow use of low ESR output capacitors.  for DCAP2, the loop gain at low frequencies is constant and phase is 180 degrees.  At the LC corner frequency, the gain starts to fall at -40 dB / dec, and phase drops rapidly from 180 degrees towards 0 degrees (since the output capacitor is low ESR ceramic type, the Q is high). There is an internal zero caused by the ripple injection circuit.  Phase will start to increase one decade below the internal zero frequency towards 90 degrees.  At the internal zero frequency phase will be 45 degrees and the gain slope will be - 20 dB / dec.  For DCAP2 the goal is to align the LC corner frequency near enough to the fixed, internal zero frequency, so that some conditions are met: phase does not drop to zero, final closed loop crossover is not to high, and phase at crossover is close to 45 degrees.  For DCAP 2, this means that for many applications measured phase margin will be less than 45 degrees.  You have to remember that "phase margin" is exactly that, it is margin, or a figure of how far away you are from instability, so the absolute value of phase margin is not so important, just the relative slope of the phase curve near crossover.  For ordinary voltage mode or current mode control, phase is usually dropping off rapidly at crossover, so phase margin is important.  For DCAP2, phase is actually INCREASING at crossover, so the circuit is inherently stable.  There is no chance of phase dropping to zero (oscillating) if the external L and C are properly chosen.  If additional phase margin is desired, you can add a FF cap across the upper resistor of the voltage setpoint divider.  This is mostly applicable to higher output voltages above 1.8 V.  I do have some powerpoint I did for another customer.  Contact me offline if you would like to see it.

Hi Rosario,

Please contact Rama Venkatraman directly. He is the system engineer for TPS51461 and should have the design tool for Rc, Cc calculation. His email address:

rama-venkat@ti.com

Thanks,

Nancy

Hi Rosario,

I gave you a wrong contact person before. You can contact Yoshikawa Miura (y-miura2@ti.com) directly. He is in charge of this part.

Thanks,

Nancy

For TPS51216, the VDDQSNS pin is equivalent to FB pin.  There is no ripple injection built in to DCAP, it relies on ripple voltage due tho ESR of output capacitors.  Yes the TPS51216 uses the SW node voltage to sense VIN.

TPS51463 senses current by measuring low side FET drain source voltage during the "off" time.  it is proportional to the current.