• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 727 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLC5944/about GS and DC shift register

Tsukui Yusuke
Guru 21930 points

Hi,

Could you tell me about GS and DC shift register DCSEL changeing timing?
Data sheet has the following description in page19 and 20.

'' A DCSEL level change is allowed when SCLK is low and 100 ns after the rising edge of XLAT.''

My customers are trying to do the above-mentioned the SCLK in SCLK is High.
Do you have any problems with changeing DCSEL in SCLK is High condition?
Could you give me your advice?
Cou



Best regards,
Yusuke/Japan Disty

  • 0
    Guru 21930 points

    Hi,

    Can I get the information?

    If you need more information or if  I should  clarify my comment ,

    please let me know.

    I’m so sorry to rush you but please support this.

    Best regards,

    Yusuke/Japan Disty

  • 0 in reply to Tsukui Yusuke
    Guru 21930 points

    Hi,

    Can I get the information?

    If you need more information or if  I should  clarify my comment ,

    please let me know.

    I’m so sorry to rush you but please support this.

    Best regards,

    Yusuke/Japan Disty

  • 0
    TI__Expert 4035 points
    Hi Yusuke,

    As we known, when DCSEL is low, SCLK/XLAT/SOUT are connected to the GS shift register and data latch, when DCSEL is high, SCLK/XLAT/SOUT are connected to the DC shift register and data latch.

    As my understanding, Grayscale Data Write Timing or Dot Correction Data Write Timing could be broken down with the changing of DCSEL when SCLK is High, then the GS data or the DC data might not the same as the Serial data you inputted, but no big problem or damage to the unit.

    "A DCSEL level change is allowed when SCLK is low and 100ns after the rising edge of XLAT" just makes a guarantee that the GS data or DC data has been written correctly.

    BRs,
    Ryan