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TPS56C215: TPS56C215 layout guidelines

Shinya Sawamoto
Expert 5285 points
Part Number: TPS56C215

Hello application team,

I have a question about TPS56C215 layout guidelines.
It has two VIN pins for both side of the package and I found a description to recommend having equal caps on each side of the IC as figure 47 on the datasheet page-27.
If it is impossible and have caps on the only one side, what is the potential concern?
I think VINs, SWs and PGNDs are connected internally on the chip, is it correct?

Thanks in advance.
Shinya Sawamoto
TI Japan East area FAE

  • 0
    TI__Mastermind 34045 points
    Shinya-san,

    The symmetric placement of Cin cap helps to reduce EMI noise, it's not mandatory, but you still need to conect two VIN pins externally with shortest and thick wire trace.

    B R
    Andy
  • 0
    TI__Expert 5745 points

    You can put the big cap (22uF) in one side, but you can't put the small cap(0.1uF) in one side, because the input ripple will have a big ring without the small cap which will also appear in the SW node. The EMI will be worse. The main reason is the Parasitic inductance oscillation. You can see the waveform as below.