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LM3445: Analog input dimming in FILTR2

user5083847
Prodigy 20 points
Part Number: LM3445

Hello! I have an issue that i haven’t seen much detail on yet (bear with me if there’s loads of info on the subject).

I am designing a 230V 200W luminaire using 4x50W (1400mA 36V) LEDs. I plan on connecting them in 2 pairs in series (stack voltage=72V) using 1 LM3445 for each pair. My issue is that i want to incorporate the dimming function within my design so i was thinking of using the FILTR2 pin as an analog input for dimming rather than depending on an external TRIAC dimmer. The description on FILTR2s function says it “Could also be used as an analog dimming input”, i was wondering what the voltage range for dimming would be? Would a simple potentiometer and resistor network voltage divider from Vcc to GND connected to the FILTR2 pin of both LM3445s work? Any other precautions to keep in mind?

I understand that DIM can be used as an input if FILTR1 is pulled above 4.9V, would that be a preferable way to dim via an external PWM generator?

Should i just design an in-board triac dimmer and leave it at that?

Thank you all in advance!

  • 0
    TI__Mastermind 28655 points

    Hello,

    You have a few options to do this per your email.  You could pwm the dim pin, you would still need the FLTR2 filter to make it DC for the peak current reference (designed per the datasheet).  You could also just use the FLTR2 pin as an analog dim.  The range would be 0-750 mV.  You have to be careful that you limit the range on FLTR2 because it can be pulled up beyond 750 mV and provide more current than the maximum calculated per the datasheet.  There is also a peak current shutdown threshold at 1.269V typical that will cause a timed shutdown so you don't want to be able to pull it that high.

    I wouldn't design an in-board triac dimmer since triac dimming is generally not as good as analog or pwm generated dimming.

    Note that this device regulates peak current so half of the 0-750 mV range, or 375 mV, will not be half the light output, it will be half of the peak current trip threshold.  The larger the inductor the closer to linear it will get since the peak to peak ripple gets smaller.

    Regards,

  • 0 in reply to Irwin Nederbragt
    Prodigy 20 points

    Dear Irwin,

    Thank you for your fast response. Indeed i did some more digging and realized the range of FILTR2 during normal operation would be between 0 and 750mv, which would correspond to a duty cycle of 25% to 75% and a conduction angle of 45° to 135°

    I also realized that the appropriate signal for PWM would be a 5.9 kHz square wave with duty cycle varying from 25% to 75% (I do not know however what amplitude it should have)

    I do have a few follow up questions, if you don’t mind that is:

    Firstly is what do i do with the line sensing pins that aren’t used anymore? I am refering to BLDR, ASNS, FILTR1 and DIM. I was thinking of leaving ASNS and DIM disconnected and tying BLDR and FILTR1 to ground, would that work?

    Secondly and not so importantly, I was wondering how to generate the 0 to 750mv analog signal, maybe some combination of rail to rail op amps together with a 12V regulator after D2 and C5 to make Vcc a little more steady (possibly also a voltage converter ic for a split rail supply?)? What do you think?

    Also thank you for the heads up on the inductor, the selected one so far is a rather beefy 1.2mH unit from Bourns. 1130-122K-RC is the part no.

    Regards, Juan

  • 0 in reply to user5083847
    TI__Mastermind 28655 points
    Hello Juan,

    So your first statement is correct, it corresponds to 25-75% of the voltage available from the triac, the 0-4 range is decoded from 1-3V giving that range.

    The second statement; it doesn't need to be 5.9 KHz and the duty cycle varies from 100 to 0% (it's inverted since it's driving an internal MOSFET gate, look at the block diagram), that way the filtered voltage would be 0-750 mV, 25% of triac waveform corresponding to 100% duty at DIM and 0V at FLTR2, 75% of triac waveform corresponding to 0% duty at DIM and 750 mV at FLTR2. The datasheet has PWM input limits at 0.9V to 3.15V worst case (1.33 and 2.33 typical).

    BLDR can be left open, ASNS can be left open, FLTR1 needs to be pulled above 4.9V to allow DIM to be a PWM input so tie to VCC. Or, if going with FLTR2 tied DIM to GND with FLTR1 still tied to VCC.

    It depends on how low you want the FLTR2 pin to go. If I were to do this I would use an op-amp and divide the output down with a resistor divider provided the output of the op-amp can go low enough for your application. The PWM input may be an easier way if that is a concern. You could also create a PWM signal and filter it and send to the FLTR2 pin. If a 0-10 volt range was used a divider of 13.3 would be needed.

    Regards,