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TPS24751EVM-546: Evaluation kit faults when J2 is used, as fault time < output rise time

Joel Cottrell
Prodigy 50 points
Part Number: TPS24751EVM-546

Hi, I've come across a problem with the evaluation kit for the TPS2475x, and I'd appreciate some TI input.

The capacitor on the TIMER pin is 47nF, which sets the fault timer to 6.35ms. (See SLVSC87B, Equation 11)
The capacitor on the GATE pin (via jumper J2) is also 47nF, which purposely slows down the rise time to ~20ms. (See SLVSC87B, Equation 15).

Since 6ms < 20ms, my oscilloscope shows that the gate pin only ever rises to a few volts before the device faults and resets. I can correct this by swapping out capacitors, making the fault timer slower and the output rise time faster, but I wasn't expecting to need to do this for an evaluation module. Is my maths correct, or have I done something wrong?

Thanks, Joel

  • 0
    TI__Guru** 101981 points
    Hi Joel,

    Thanks for bringing this to our notice.
    Your calculations are correct. One of the capacitor values C2 or C6 needs to be changed to make it testable for rise time. We will take action to correct it in the next board spin.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 50 points
    Hi Rakesh,

    Thank you , it's good to have verification that I've understood correctly.

    I have substituted: C2 = 30nF, C6 = 200nF
    This gives ~15ms rise time for my application and doesn't fault out.

    Thanks, Joel