Hi, I've come across a problem with the evaluation kit for the TPS2475x, and I'd appreciate some TI input.
The capacitor on the TIMER pin is 47nF, which sets the fault timer to 6.35ms. (See SLVSC87B, Equation 11)
The capacitor on the GATE pin (via jumper J2) is also 47nF, which purposely slows down the rise time to ~20ms. (See SLVSC87B, Equation 15).
Since 6ms < 20ms, my oscilloscope shows that the gate pin only ever rises to a few volts before the device faults and resets. I can correct this by swapping out capacitors, making the fault timer slower and the output rise time faster, but I wasn't expecting to need to do this for an evaluation module. Is my maths correct, or have I done something wrong?
Thanks, Joel