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TPS2660: Criteria A surge performance

tom
Prodigy 200 points
Part Number: TPS2660

Hi,

Application note SLVA833A mentions the possibility for criteria A surge performance with the TPS2600.

I would like to request the information to implement this.

Surge level is according to IEC 61000-4-5: +-500 V, 2Ω impedance.

best regards,

Tom

  • 0
    TI__Genius 16305 points
    Hi Tom,

    TPS2660 eFuse provides protection to downstream during surge tests, it cuts off power path so that over voltage is not propagated to downstream.
    Power path is cutoff by turning of the internal FETs to protect the downstream circuits.
    During this time, capacitor at the output of eFuse discharges based on the load.
    If the capacitor is not enough to hold the load long enough, before the eFuse recovers, downstream circuits will turn off due to their own UVLO.
    For heavy loads, back up supply may have to designed additionally.

    After the overvoltage due to surge is settled, eFuse tries to restart based on the UVLO turn on delay.
    This delay can be overcome by adding a resistor in series to dVdT capacitor placed on dVdT pin of the IC.

    Next, during the surge, Voltage across IN-OUT of eFuse should not exceed 70V. TVS has to be selected based on the surge level.

    For Criteria A, please refer to the TI design "www.ti.com/.../TIDA-03031"

    Regards,
    Kari.
  • 0 in reply to Karikalan Selvaraj
    Prodigy 30 points

    Hi Kari,

    In the slva833a application note there is also an example for 10ms power interuption with just a 2mF hold-up capacitor.
    I think this will be sufficient for our application, i just have two questions:
    1. How is the value of the resistor in series to DvDt determined?
    2. #Fault signal stays low until hold-up capacitor is fully charged with current limit after surge + tPGOODR delay right? (probably in the order of 5-10ms).

    best regards,
    Tom