Hi team
I designed the schematic as above.
Please check that there are no problems.
Thanks,
taemin
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Hi team
I designed the schematic as above.
Please check that there are no problems.
Thanks,
taemin
Hi Richard
Thank you very much for your dedicated help.
It has helped a lot.
Thanks,
Taemin
Hello Taemin,
The advice I provided on the previous post still applies, regarding the sizing of the bootstrap capacitor, VDD capacitor, and Mosfet & driver selection depending on operating at high frequency.
One additional recommendation, as good design practice, will be to add some resistance from the gate to source of the MOSFETs to address any leakage current from drain to source during power up of the control and driver bias.
Can you confirm on the thread if this addresses your questions?
Regards
Richard Herring