TLC5957: how to reduce the FPGA resouces

There are two  working modes of TLC5957 : Traditional Mode and Poker Mode.Now the Traditional mode is used.This mode USES 16-bit grayscale mode, resulting in too long time of grayscale scanning. We will use Poker mode now, but the data packaging of this mode is relatively random, which requires a large amount of FPGA resources. The current FPGA resources are not enough to support this mode.We now want to know if TI has a frugal resource implementation for Poker mode? Thanks