Good morning,
On the design of a PWM converter, I am interested in knowing the minimum Vds pulse width that the integrated GaN+driver can reproduce. This will help me know the supply voltage range I can expect to control adequately.
From the datasheet, adding the stated tpd,on + tdelay,on = 32ns. I understand that that is the minimum pulse width that will propagate. Is this correct?
Therefore, with a 40ns input pulse, taking into account tpd,on + tdelay,on + tVDS,ft = 36.2ns , a 4ns drain source pulse should be expected ?
Kind regards,