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LMG3411R070: Minimum drain-source pulse width for MHz operation

Part Number: LMG3411R070

Good morning, 

On the design of a PWM converter, I am interested in knowing the minimum Vds pulse width that the integrated GaN+driver can reproduce. This will help me know the supply voltage range I can expect to control adequately.

From the datasheet, adding the stated tpd,on + tdelay,on = 32ns. I understand that that is the minimum pulse width that will propagate. Is this correct?

Therefore, with a 40ns input pulse, taking into account  tpd,on + tdelay,on + tVDS,ft = 36.2ns , a 4ns drain source pulse should be expected ?

Kind regards,

  • Hello,

    Here I think you are mainly talking about the delay match of the driver. In addition to that, GaN switching speed is set by the RDRV resistor and the load current. You can control those in your system. With  a small input pulse width, you can get the Vds waveform to be a triangle shape. The falling-edge is set by RDRV and the rising edge is set by the load current.

    Thanks and regards,

    Lixing